Avnera Corporation

Intel Corporation

Skyworks Solutions, Inc.

Xudong Zhao

Amit Kumar

Ron Nevo

Thomas Irrgang

Wai Laing Lee

Garry Link

Alexander C Stange

Chris O'Connor

Ephraim Zehavi

Jianping Wen

Ran Ginosar

Eric T King

Shawn O'Connor

Michael Vakulenko

Ali Hadiashar

Miles Reuben Thompson

Rie Sasakawa

Dror Shindelman

Enhraim Zehavi

In some embodiments, a wireless network architecture can include a network protocol configured to allow communication between a host device and each of an audio device and a human interface device. The network protocol can include a transaction having a time duration, with the transaction including a plurality of sub-transactions arranged in sequence. Each sub-transaction can have a time duration and a frame for the human interface device such that a latency period associated with the human interface device is greater than or equal to the time duration of the sub-transaction but less than the time duration of the transaction.

Systems, devices and methods related to wireless network having low latency

In some embodiments, a digital-to-analog converter (DAC) architecture can include an array having a total number of bit cells, and a control system configured to activate a selected number of the total number of bit cells and to deactivate the remaining bit cells. The selected number can be variable, such that the array consumes a quiescent current that depends on the selected number. The control system can be further configured to change the selected number when a signal condition exceeds a threshold duration.

Digital-to-analog converter architecture for audio amplifiers

Embodiments of the invention may be used to implement a rate converter that includes: 6 channels in forward (audio) path, each channel having a 24-bit signal path per channel, an End-to-end SNR of 110 dB, all within the 20 Hz to 20 KHz bandwidth. Embodiment may also be used to implement a rate converter having: 2 channels in a reverse path, such as for voice signals, 16-bit signal path per channel, an End-to-end SNR of 93 dB, all within 20 Hz to 20 KHz bandwidth. The rate converter may include sample rates such as 8, 11.025, 12, 16, 22.05, 24, 32 44.1, 48, and 96 KHz. Further, rate converters according to embodiments may include a gated clock in low-power mode to conserve power.

Rate converter

An audio processing system can include an Analog to Digital Converter structured to receive an analog input signal and convert the analog input signal to a digital input signal, a first processor coupled with the Analog to Digital Converter, the first processor including at least one programmable bi-quadratic filter chain structured to receive the digital input signal from the Analog to Digital Converter and perform audio processing on the received digital input signal at a first clock rate, and a second processor coupled with the first processor and the Analog to Digital Converter and structured to receive the digital input signal from the Analog to Digital Converter and perform audio processing on the received digital input signal at a second clock rate that is different from the first clock rate.

Acoustic processor having low latency

A low power, digital audio interface includes support for variable length coding depending on content of the audio data sent from the interface. A particularized coding system is implemented that uses techniques of silence detection, dynamic scaling, and periodic encoding to reduce sent data to a minimum. Other techniques include variable packet scaling based on an audio sample rate. Differential signaling techniques are also used. The digital audio interface may be used in a headphone interface to drive digital headphones. A detector in the interface may detect whether digital or analog headphones are coupled to a headphone jack and drive the headphone jack accordingly.

Low power synchronous data interface

A Class G amplifier system including a processing unit configured to receive an input signal and output a delayed processed input signal, a class G amplifier configured to receive the delayed processed input signal, and a power supply. The power supply includes a regulator configured to operate in a plurality of configurations, each configuration outputs a different supply voltage to the class G amplifier and a control circuit configured to receive the input signal and determine the supply voltage required from the regulator when the delayed processed input signal is received at the class G amplifier, and output a signal to the regulator to indicate the required configuration for the required supply voltage.

Power supply for class G amplifier

A system for detecting and capturing voice commands, the system comprising a voice-activity detector (VAD) configured to receive a VAD-received digital-audio signal; determine the amplitude of the VAD-received digital-audio signal; compare the amplitude of the VAD-received digital-audio signal to a first threshold and to a second threshold; withhold a VAD interrupt signal when the amplitude of the VAD-received digital-audio signal does not exceed the first threshold or the second threshold; generate the VAD interrupt signal when the amplitude of the VAD-received digital-audio signal exceeds the first threshold and the second threshold; and perform spectral analysis of the VAD-received digital-audio signal when the amplitude of the VAD-received digital-audio signal is between the first threshold and the second threshold.

Low-power, always-listening, voice command detection and capture

An audio system can include an analog portion having multiple input sensors and an output device, a first digital portion running at a first rate and having a first processor that is electrically coupled with the input sensors and the output device, and a second digital portion running at a second rate that is higher than the first rate and having a second processor that is electrically coupled with the first processor.

Rate convertor

An audio system having low latency includes a digital audio processor as well as sensor inputs coupled to the processor. The sensor inputs may be microphone inputs. The audio processor operates at the same frequency as the sensor inputs, which is typically much higher than an audio signal provided to the audio processor. In some aspects the audio processor operates as a noise cancellation processor and does not include an audio input.

A multi-protocol wireless apparatus is provided with at least one wireless transceiver to transmit and receive signals in accordance with a first and a second protocol to and from first and second network devices of a first and a second wireless network communicatively coupled to the apparatus. The apparatus is further provided with at least one controller manager to operate the at least one wireless transceiver to perform the transmits and receives in accordance with the first and second protocols in a coordinated manner, taking into consideration quality of service criteria to be achieved for the respective protocols.

Multiple wireless communication protocol methods and apparatuses including quality of service considerations

A radio receiver channel includes an analog front end and a digital signal processing section coupled together by an analog-to-digital converter (ADC) having a delta-sigma modulator coupled to a first digital decimation filter, which is coupled to second digital decimation filter, wherein the first decimation filter includes a source of finite impulse response coefficients coupled so as to provide a plurality of coefficients. The delta-sigma modulator includes a loop filter having a plurality of serially coupled integrators, and a multi-bit quantizer coupled to the loop filter; the multi-bit quantizer including an ADC operable to produce a multi-bit digital output signal, the ADC coupled to a DAC having dual DAC feedback loops, and a dynamic element matching function. In one embodiment, the delta-sigma modulator includes a fifth-order loop filter having five serially coupled integrators with a feedback path from the output to the input of the fifth integrator and a feedback path from the output to the input of the third integrator.

Delta-sigma analog-to-digital converter suitable for use in a radio receiver channel

Techniques for supporting multiple potentially overlapping wireless protocols with a single electronic system are disclosed. In the description that follows, the overlapping protocols are Bluetooth and IEEE 802.11 for wireless networking; however, other overlapping protocols can be supported in a similar manner. A transaction control policy and a collision map are provided to determine which protocol to enable/disable when a conflict arises. Based on the transaction control policy and the collision map, one or more transceivers that operate according to the wireless protocols can be selectively enabled/disabled to avoid actual conflicts.

Growing community of inventors

Portland, OR, United States of America

Xudong Zhao