International Business Machines Corporation

Xudong Wang

John Joseph Pekarik

Xiaodong Wang

Robert Mark Rassel

Marwan H Khater

Gregory Gower Freeman

Anil Kumar Chinthakindi

David R Greenberg

Basanth Jagannathan

Frederick Gustav Anderson

Nicholas Theodore Schmidt

Structure and methods for a differential junction varactor. The structure includes: a silicon first region formed in a silicon substrate, the first region of a first dopant type; and a plurality of silicon second regions in physical and electrical contact with the first region, the plurality of second regions spaced apart and not in physical contact with each other, the plurality of second regions of a second dopant type, the first dopant type different from the second dopant type; a cathode terminal electrically connected to the first region; a first anode terminal electrically connected to a first set of second regions of the plurality of second regions; and a second anode terminal electrically connected to a second set of second silicon regions of the plurality of second regions, second regions of the first set of second regions alternating with second regions of the second set of second regions.

Differential junction varactor

A method of forming a current mirror device for an integrated circuit includes configuring a reference current source; forming a first field effect transistor (FET) in series with the reference current source, the first FET of a first conductivity type formed on a first portion of a substrate having a first crystal lattice orientation; and forming a second FET of the first conductivity type on a second portion of the substrate having a second crystal lattice orientation, with a gate terminal of the first FET coupled to a gate terminal of the second FET, and the gate terminals of the first and second FETs coupled to the reference current source; wherein the carrier mobility of the first FET formed on the first portion of the substrate is different than the carrier mobility of the second FET formed on the second portion of the substrate.

Method and apparatus for improving integrated circuit device performance using hybrid crystal orientations

A method for implementing a desired offset in device characteristics of an integrated circuit includes forming a first device of a first conductivity type on a first portion of a substrate having a first crystal lattice orientation, and forming a second device of the first conductivity type on a second portion of the substrate having a second crystal lattice orientation. The carrier mobility of the first device formed on the first crystal lattice orientation is greater than the carrier mobility of the second device formed on the second crystal lattice orientation.

A field effect transistor is provided which includes a contiguous single-crystal semiconductor region in which a source region, a channel region and a drain region are disposed. The channel region has an edge in common with the source region as a source edge, and the channel region further has an edge in common with the drain region as a drain edge. A gate conductor overlies the channel region. The field effect transistor further includes a structure which applies a stress at a first magnitude to only one of the source edge and the drain edge while applying the stress at no greater than a second magnitude to another one of the source edge and the drain edge, wherein the second magnitude has a value ranging from zero to about half the first magnitude. In a particular embodiment, the stress is applied at the first magnitude to the source edge while the zero or lower magnitude stress is applied to the drain edge. In another embodiment, the stress is applied at the first magnitude to the drain edge while the zero or lower magnitude stress is applied to the drain edge.

Field effect transistor having an asymmetrically stressed channel region

An oscillator for generating a fundamental frequency signal and harmonic signal to provide multiple radio frequency signals. First and second bipolar transistors are differentially connected, and have base and collector terminals cross-coupled. A pair of inductors serially connect the collectors of the transistors to one terminal of a d.c. power supply source. A current source connects to the other terminal of the d.c. power supply source and to the emitters of the differentially connected transistor. A tuning capacitor connected between collector terminals establishes a resonant frequency for the oscillator. Crosscoupling is affected at a level that produces harmonic signals which can be used along with a fundamental frequency signal in numerous radio telecommunications applications.

Dual frequency voltage controlled oscillator circuit

A cross-coupled voltage controlled oscillator having reduced phase noise. A pair of bipolar transistors having common emitter connections are coupled to reduce that oscillation frequency which is determined from a tuning circuit connected across the collectors of transistors. First and second varactor diodes provide analog tuning of the circuit, and a digitally controlled capacitor provides for a selection of a band of frequencies to be tuned by the varactor diodes. A current source provides the current to the emitter connections of the bipolar transistors. Second harmonic signals generated at the emitter of the transistors are significantly suppressed by a tuned filtered trap connected to the common emitter connections. By reducing the second harmonic signals, the phase noise or the voltage controlled oscillator can be significantly improved.

Growing community of inventors

Groton, MA, United States of America

Xudong Wang