Rambus Inc.

Google Inc.

Altera Corporation

Xudong Shi

Huy M Nguyen

Kambiz Kaviani

Reza Navid

Jason Chia-Jen Wei

Scott C Best

Wilson Wong

Weiqi Ding

Arif Abdulhusein Merchant

Kun-Yung Chang

Fariborz Assaderaghi

Jie Shen

Wei Li

Christian Eric Schrock

Murray M Stokely

Yueyong Wang

Wangyuan Zhang

Sangho Yoon

Pramod Gaud

Christoph Albrecht

Vivienne Zhang

Kaifeng Yao

A system and method for storing data in a distributed network having a plurality of datacenters distributed over a plurality of geographic regions. The method may involve receiving data, including metadata, uploaded to a first datacenter of the distributed network, receiving access information about previous data that was previously stored in the plurality of datacenters of the distributed network, predicting one or more of the plurality of geographic regions from which the uploaded data will be accessed based on the metadata and the access information, and instructing the uploaded data to be transferred from the first datacenter to one or more second datacenters located at each of the one or more predicted geographic regions.

Access pattern driven data placement in cloud storage

The common-mode input voltage of a common-gate input amplifier receiving a differential signal is set in an open-loop manner by basing the bias current and/or source load impedances of the common-gate amplifier on a transmitter bias current and driving impedance. The common-mode input voltage of a common-gate input amplifier receiving a differential signal may be set in a closed-loop manner using a feedback loop having a captured target voltage compared to the common-mode input voltage at a node of the amplifier. The common-mode input voltage of a common-gate input amplifier receiving a differential signal may be set in a continuous time closed loop manner by sending a reference current through resistances that are multiples of a resistance used to generate the reference current.

Common mode calibration

A method of equalizing an input data signal using a multiple-stage continuous-time linear equalization (CTLE) circuit. A zero-forcing least-mean-square (ZF LMS) procedure is applied to adapt the settings of the CTLE stages. The amplitude settings and the frequency boost settings of the CTLE stages are adapted within the ZF LMS procedure. In an exemplary implementation, an error screening threshold may be applied to an error signal within the ZF LMS procedure to generate a reduced error signal such that weight updates do not occur if the error signal is below the error screening threshold. In addition, if an accumulated sign error signal within the ZF LMS procedure reaches a predetermined maximum indicative of a high loss channel, then a setting for a variable gain amplifier may be increased, and an amplitude setting for the CTLE circuit may be decreased. Other embodiments, aspects and features are also disclosed.

Methods and apparatus for multiple-stage CTLE adaptation

Systems and methods are discussed relating to allocation of memory from a fixed pool of fast memory within a data center having a data storage area equipped with that memory. Techniques include: receiving a request to write data in the storage area; identifying a file group associated with the write request; analyzing previous data activity traces associated with the file group; determining an available fast memory amount based on the total amount of fast memory in the fixed pool and a currently allocated amount of fast memory; determining a fast memory allocation for the file group based on the previous data activity traces, the available fast memory, and a fast memory constraint, the memory allocation including an allocation amount and a write probability; and providing information about the memory allocation to a file system of the data center, which writes the data based on the allocation amount and write probability.

Optimizing allocation of flash memory to file groups

Differential receivers are 'stacked' and independently calibrated to different common-mode voltages. The different common-mode voltages may correspond to the common-mode voltages of stacked transmission circuits. Multiple stacks of samplers are connected to the same channels. The clocking of each stack of sampler circuits is phased (timed) such that the samplers in a given stack are not resolving at the same time. Samplers in a different stack and receiving a different common-mode voltage resolve at the same time.

Stacked receivers

A PLL/DLL circuit is current self-biased responsive to a current Iprovided from a voltage regulator to a VCO or VCDL. Bias current I, which is proportional to I, is provided to components of the PLL/DLL, such as a charge pump or loop resistor, from an interconnect coupled to the voltage regulator. In an embodiment of the present invention, a component of the PLL/DLL includes a bias-generating device, such as a MOSFET p-type transistor having a drain coupled to the interconnect. In an embodiment of the present invention, a voltage regulator includes an AMP having a bias-generating device, such as a p-type transistor, acting as a current source, having a source coupled to Vand a drain coupled to the interconnect. The gate of the bias-generating device is coupled to the gate of four other p-type devices. Each of the four p-type devices has a source coupled to V. The drains of the first and second p-type transistors are coupled to an output providing I. A negative input of the AMP ('INM') is coupled to the gate of a first n-type transistor and a positive input of the AMP ('INP') is coupled to the gate of a second n-type transistor. The drains of the first and second n-type transistors are coupled to the drains of the second and third p-type transistors. The sources of the first and second n-type transistors are coupled to the drain of a third n-type transistor. The source of the third n-type transistor is coupled to ground and the gate is coupled to a fourth n-type transistor. The drain of the fourth n-type transistor is coupled to the drain of the fourth p-type transistor and the source of the fourth n-type transistor is coupled to ground.

Regulated adaptive-bandwidth PLL/DLL using self-biasing current from a VCO/VCDL

A circuit includes a phase interpolator and a self test circuit. The phase interpolator is to provide a interpolator output having a phase corresponding to a respective phase step in a plurality of phase steps. The interpolator output is a weighted combination of one or more of a plurality of phasor signals. The self test circuit includes a phase detector coupled to a reference signal and the interpolator output, a phase-difference-to-voltage converter coupled to the phase detector, an analog-to-digital converter (ADC) coupled to the phase-difference-to-voltage converter, and control logic. The phase detector is to generate an output that is proportional to a phase difference between the reference signal and the interpolator output. The phase-difference-to-voltage converter is to convert the output from the phase detector into a corresponding voltage. The ADC is to convert an output from the phase-difference-to-voltage converter into a corresponding digital value. The control logic is to test the phase interpolator using the self-test circuit.

Phase linearity test circuit

A pre-driver circuit for use in high speed signaling systems is disclosed. In one particular exemplary embodiment, the pre-driver circuit may comprise an input transistor, an active load, a passive load, and a current source. The input transistor has a gate terminal, a current sinking terminal, and a current sourcing terminal. The active load has a control input coupled to the gate terminal of the input transistor, a current sourcing terminal coupled to the current sinking terminal of the input transistor, and a current sinking terminal. The passive load has a first terminal coupled to the current sinking terminal of the active load and a second terminal coupled to the current sourcing terminal of the active load. The current source is coupled to the current sourcing terminal of the input transistor.

Pre-driver circuit

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Sunnyvale, CA, United States of America

Xudong Shi