Advanced Micro Devices Corporation

Boe Technology Group Co., Ltd.

Chengdu Boe Optoelectronics Technology Co., Ltd.

Xudong An

Wei T Huang

Karthik Rao

Zhen Zhang

Yasuko Eckert

Junjie Zhao

Shomit N Das

Jieming Yin

Muhammad Shoaib Bin Altaf

Wei Peng Huang

Fei Fei Li

Joseph Lee Greathouse

Manish Arora

Xinwei Wu

Yuqing Yang

Lei Deng

Yue Wei

Fuwei Zou

Kangguan Pan

Huimin Cao

Xia Tang

Guangzhou Zhao

Xijie Peng

Lin Wen

In some examples, thermal aware optimization logic determines a characteristic (e.g., a workload or type) of a wavefront (e.g., multiple threads). For example, the characteristic indicates whether the wavefront is compute intensive, memory intensive, mixed, and/or another type of wavefront. The thermal aware optimization logic determines temperature information for one or more compute units (CUs) in one or more processing cores. The temperature information includes predictive thermal information indicating expected temperatures corresponding to the one or more CUs and historical thermal information indicating current or past thermal temperatures of at least a portion of a graphics processing unit (GPU). The logic selects the one or more compute units to process the plurality of threads based on the determined characteristic and the temperature information. The logic provides instructions to the selected subset of the plurality of CUs to execute the wavefront.

Apparatus and method for providing workload distribution of threads among multiple compute units

A backplane, a display device and a method of manufacturing a backplane are provided. The backplane includes a base substrate; an inorganic layer on the base substrate, the inorganic layer including a plurality of protrusions; a metal layer covering atop of each protrusion and partial side wall near the top, the metal layer covering adjacent protrusions being disconnected; and a light-emitting layer covering the metal layer and the inorganic layer between the adjacent protrusions, the light-emitting layer being disconnected at regions of the protrusions not covered by the metal layer.

Display backplane with metal layer on protrusions

A plurality of thermal electric cooler (TEC) elements are formed in a TEC grid structure. Control logic dynamically varies a supply current supplied to each TEC element (or group of TEC elements) in the TEC grid based on changes in power density respectively associated with areas cooled by each of the TEC elements or group of TEC elements.

Runtime localized cooling of high-performance processors

A method of fabricating a substrate is provided. The method of fabricating the substrate includes forming a first conductive pattern; forming a first insulating layer, and forming a first blind hole in the first insulating layer; forming a conductive film layer, and removing at least a portion of the conductive film layer in the first blind hole; thinning a portion of the first insulating layer at a bottom of the first blind hole to form a second blind hole; forming an intermediate insulating layer, and forming a second via hole in the intermediate insulating layer; removing the portion of the first insulating layer and forming a first via hole in the first insulating pattern layer; and forming a second conductive pattern. The second conductive pattern directly contacts the first conductive pattern through the first via hole and the second via hole and insulates from the intermediate conductive pattern.

Substrate and fabricating method thereof, and display apparatus

The described embodiments include an apparatus that controls voltages for an integrated circuit chip having a set of circuits. The apparatus includes a switching voltage regulator separate from the integrated circuit chip and two or more low dropout (LDO) regulators fabricated on the integrated circuit chip. The switching voltage regulator provides an output voltage that is received as an input voltage by each of the two or more LDO regulators, and each of the two or more LDO regulators provides a local output voltage, each local output voltage received as a local input voltage by a different subset of the circuits in the set of circuits. During operation, a controller sets an operating point for each of the subsets of circuits based on a combined power efficiency for the subsets of the circuits and the LDO regulators, each operating point including a corresponding frequency and voltage.

Setting operating points for circuits in an integrated circuit chip

Growing community of inventors

Austin, TX, United States of America

Xudong An