Washington University

University of Florida Research Foundation, Incorporated

Meta Platforms, Inc.

Xuan Zhang

Lan Yang

Hsien-Hsin Sean Lee

Yier Jin

Weidong Cao

Carole-Jean Wu

Weijian Chen

Udit Gupta

Ayan Chakrabarti

Mark David Hempstead

Yichen Jiang

Xiaolong Guo

Liu Ke

Brandon Reagen

Huifeng Zhu

Embodiments provide for predicting rowhammer attack vulnerability of one or more memory cells of a direct random access memory (DRAM) chip, the DRAM chip including a plurality of memory cells. An example method, determines, for each memory cell of a subset of memory cells of the plurality of memory cells, a leakage time t, a resistance of intrinsic leakage Rbased at least in part on the leakage time t, an activation time of an adjacent aggressor row to flip a bit in the memory cell, a resistance of coupling leaking Rbased at least in part on the activation time, and a toggling count. The method identifies, based at least in part on one or more of the R, R, or toggling count, whether the direct random memory access (DRAM) chip is vulnerable to a rowhammer attack.

Fast and efficient system and method for detecting and predicting rowhammer attacks

An integrated circuit is disclosed. The integrated circuit includes a first resonator, a second resonator, and a coupling element. The first resonator has a first terminal and a second terminal, where the first resonator comprises a gain resistor, a gain capacitor, and a gain inductor in parallel and electrically coupling the first terminal with the second terminal. The second resonator has a third terminal and a fourth terminal, where the second resonator includes a loss resistor, a loss capacitor, and a loss inductor in parallel and electrically coupling the third terminal with the fourth terminal. The coupling element selectively couples the first terminal of the first resonator with the third terminal of the second resonator.

Fully integrated parity-time symmetric electronics

A device (e.g., an application-specific integrated circuit chip) includes a memory module processing unit and an interface. The memory module processing unit is configured to receive an instruction to obtain values stored in one or more memory components and process the obtained values to return a processed result. The memory module processing unit is also configured to store the obtained values in a cache based on one or more criteria. The memory module processing unit is configured to be included on a computer memory module configured to be installed in a computer system. The interface is configured to communicate with the one or more memory components included on the computer memory module.

Computer memory module processing device with cache storage

A neural network based learning system for designing a circuit, the design system including at least one memory, at least one processor in communication with said at least one memory, said at least one processor configured to generate a mathematical model of the circuit, determine a structural definition of the circuit from the mathematical model, define a mapping of a plurality of components of the circuit to a plurality of neurons representing the plurality of components of the circuit using at least the structural definition, synthesize, on a hardware substrate, the plurality of neurons, and execute, using the synthesized plurality of neurons on the hardware substrate, at least one test using at least one optimization constraint to determine an optimal arrangement of the plurality of components.

System and method using neural networks for analog-to-information processors

Growing community of inventors

St. Louis, MO, United States of America

Xuan Zhang