Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Xuan Tian

Liang Li

Vincent Yin

Dandan Yi

Jiahui Yuan

Henry Chin

Jojo Xing

Guanhua Yin

Yan Li

Yanli Zhang

Ming Hsi Wang

Alan David Bennett

Wei Zhao

Hua-Ling Cynthia Hsu

Loc Tu

Fanglin Zhang

Ming Wang

Zhen Qin

Yinfeng Yu

Yongke Sun

Tony Zou

A non-volatile storage apparatus comprises memory cells organized into multiple planes. To prevent one plane from disturbing another plane while concurrently programming memory cells in a first plane and memory cells in a second plane, the system determines that the memory cells in the second plane are programming slower than the memory cells of the first plane, tests whether the memory cells in the first plane have threshold voltages greater than a test level that is higher than a target verify level, determines that the memory cells in the first plane failed programming if more than a maximum number of the memory cells in the first plane have threshold voltages greater than the test level, and determines that the memory cells in the second plane failed programming if not more than a maximum number of the memory cells of the fast plane have threshold voltages greater than the test level.

Non-volatile memory with enhanced early program termination mode for neighbor plane disturb

Technology is disclosed herein compensating for neighbor memory cell interference on a target memory cell when reading the target memory cell. The voltage that is applied to the bit line associated with the target memory cell may have a magnitude that depends on the data state of the neighbor memory cell. The magnitude of the voltage on the bit line may impact the amount of drain-induced barrier lowering (DIBL) experienced by the target memory cell. The amount of DIBL may be used to provide a desired amount of compensation for the neighbor memory cell interference. A higher bit line voltage may be used to create a greater amount of DIBL and therefore greater amount of compensation for neighbor memory cell interference.

Fast direct look ahead read mode in a memory device

A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to word lines and disposed in memory holes. The memory holes are arranged in rows comprising strings which are grouped into blocks comprising a first plane and a second plane. A control means is configured to program memory cells of the first plane and the second plane connected to one of the word lines using iterations of a program operation. The control means terminates programming of the first plane prior to completing programming of the first plane in response to determining the first plane programs slower than the second plane by a predetermined number of the iterations of the program operation. The control means adjusts the predetermined number of the iterations based on an additional verify iteration performed on at least some of the memory cells beyond the iterations of the program operation.

Smart early program termination algorithm for neighbor plane disturb countermeasure

Technology for managing non-volatile memory. A bitmap may be maintained in NAND memory cells. The bits in the bitmap map to an address (e.g., PBA) in the NAND memory cells. Each bit has either a first value to indicate that the corresponding address stores valid data or a second value to indicate that the corresponding address does not store value data. Garbage collection may be performed based on the bitmap. Bit-level memory operations are performed to maintain the bitmap. Bit-level erase may be performed to erase a memory cell to have a value that indicates a valid/invalid status. The bitmap may contain unencoded data. In one aspect, a one's complement to the bitmap is stored in the NAND memory cells. The one's complement has opposite values as the regular bitmap. The system may compare the values in the regular bitmap and the one's complement bitmap for data integrity.

Non-volatile memory bitmap for garbage collection

In addition to word line related short circuits within the blocks of the array structure of a non-volatile memory device, such as NAND memory, word line related shorts can also occur in the routing for supplying the word lines of the memory blocks. Depending on the layout of the routing, some shorts for the word lines associated with one block can affect other blocks of the memory array. In particular, if the routing of a pair of adjacent local supply lines are adjacent to a global supply line, a short between the pair of adjacent local supply lines for one block can lead, through the global supply line, to defects in another of the block. Techniques are presented for detecting these layout related problematic word lines.

Non-volatile memory with layout adaptive problematic word line detection

A stack of alternating layers of dielectric and conductive materials are formed on a substrate. A first portion of the stack of alternating layers forms a plurality of blocks of NAND memory. A second portion of the stack of alternating layers forms a configurable capacitor structure. The configurable capacitor structure is configurable to form one or more capacitors of configurable capacitance.

Configurable capacitors with 3D non-volatile array

In some situations, a leak on a wordline may be a localized problem that causes data loss in a block that contains the wordline. In other situations, such as when the leak occurs near a peripheral wordline routing area, the leak can affect the entire memory die. The storage system provided herein has a fatal wordline leak detector that determines the type of leak and, accordingly, whether just the block should be retired or whether related blocks should be retired.

Storage system and method for proactive die retirement by fatal wordline leakage detection

A non-volatile storage apparatus comprises a plurality of memory cells that store host data and two models, a control circuit for writing to and reading from the memory cells, and an inference circuit. The inference circuit uses the first model with a first set of one or more metrics describing current operation of the non-volatile storage apparatus to make a first level prediction about defects and uses the second model with a second set of one or more metrics describing current operation of the non-volatile storage apparatus to make a second level prediction about defects. In one embodiment, the first level prediction is faster to make and uses less data collection, but is not as reliable, as the second level prediction. While second level prediction is more reliable, it takes more time to perform and requires a more intensive data collection, so it is only used when needed.

Non-volatile memory integrated with artificial intelligence system for preemptive block management

The memory device includes a memory block with an array of memory cells. The memory device also includes control circuitry that is in communication with the memory cells. The control circuitry is configured to program a group of the memory cells in a programming operation that does not include verify to obtain a natural threshold voltage (nVt) distribution, calculate an nVt width of the nVt distribution, compare the nVt width to a threshold, and identify the memory block as being vulnerable to cross-temperature read errors in response to the nVt width exceeding the threshold.

Techniques for checking vulnerability to cross-temperature read errors in a memory device

The memory device includes a plurality of memory cell that arranged in an array, which includes a plurality of channels that are in electrical communication with a source line. The memory device also includes a controller that is configured to erase the memory cells in at least one erase pulse. During the at least one erase pulse, the controller is configured to drive the source line to an elevated voltage that is equal to an erase voltage Vera plus a kick voltage V_kick for a duration t_kick. The controller is then configured to reduce the voltage of the source line to the erase voltage Vera such that a voltage of the channel remains elevated during the entire erase pulse, including after the voltage of the source line has been reduced to the erase voltage Vera.

Voltage kick for improved erase efficiency in a memory device

Countermeasure method for programming a non-defective plane of a non-volatile memory experiencing a neighbor plane disturb, comprising, once a first plane is determined to have completed programming of a current state but where not all planes have completed the programming, a loop count is incremented and a determination is made as to whether the loop count exceeds a threshold. If so, programming of the incomplete plane(s) is ceased and programming of the completed plane(s) is resumed by suspending the loop count and bit scan mode, and, on a next program pulse, applying a pre-determined rollback voltage to decrement a program voltage bias. The loop count and bit scan mode are resumed once a threshold voltage level equals a program voltage bias when the loop count was last incremented. BSPF criterion is applied for each programmed state. Advancement to the next loop only occurs if a programmed state is determined incomplete.

Countermeasure modes to address neighbor plane disturb condition in non-volatile memory structures

Apparatuses and techniques are described for detecting and compensating for a set of memory cells having a slow program speed, based on a comparison between the number of program loops used to complete programming for different data states. A program loop (PL) number is stored when programming is completed for memory cells of each assigned data state. The PL number of an nth state is then compared to the PL number of another state such as the n&#x2212;1st state. If the difference between the PL numbers exceeds a threshold, the set of memory cells is considered to be slow programming and a compensation is triggered. The compensation can involve increasing the program pulse width in each remaining program pulse of the program operation. In another approach, the compensation can be triggered and subsequently deactivated in the program operation.

Self-adaptive program pulse width for programming 3D NAND memory

An apparatus is provided that includes a plurality of non-volatile memory cells and a control circuit coupled to the non-volatile memory cells. The control circuit is configured to perform a first program-verify iteration on a first set of non-volatile memory cells coupled to a first word line to determine a first starting program voltage that programs the first set of the non-volatile memory cells to a first programmed state, and program a second set of non-volatile memory cells coupled to the first word line beginning with the first starting program voltage only if a defect condition does not exist.

Apparatus and methods for smart verify with neighbor plane disturb detection

Apparatuses and techniques are described for recovering from errors in a read operation. When a read operation results in an uncorrectable read error, recovery read operations are performed for each read voltage of a page of data. Each recovery read operation uses a different timing. The different timings can involve a time period which is allocated for a voltage transition, such as a settling time of a word line or bit line voltage, or a time allocated for an under kick or over kick of a word line or bit line voltage. An error count is obtained for each different timing, and an optimum timing is determined based on the lowest error count. A retry read operation is performed in which an optimum timing is used for the voltage transition for each read voltage of the page.

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Shanghai, China

Xuan Tian