Nxp B.v.

Nxp Usa, Inc.

Xu Zhang

Siamak Delshadpour

Ahmad Yazdi

Xiaoqun Liu

Jong Myoung Kim

Ronald Dean Smith

David Edward Bien

Kenneth Jaramillo

Xueyang Geng

James Raymond Spehar

Jason Ryan Ferguson

Harold Garth Hanson

Anu Mathew

Ranjeet Kumar Gupta

Soon-Gil Jung

Tong Liu

Samuel Michael Palermo

Mikhail Svoiski

Cornelis Johannes Speelman

Embodiments of redrivers and resistive termination units for redrivers are disclosed. In an embodiment, a resistive termination unit for a redriver includes a resistor connected to an input/output terminal of the redriver, a first switch connected to the resistor and to a supply voltage of the redriver, a second switch connected to the first switch and configured to be turned on or off in response to a change in the supply voltage of the redriver, and a control circuit connected to the first switch through the second switch and configured to generate a control signal for the first switch.

Redriver and resistive termination unit for a redriver

Embodiments of equalizers are disclosed. In an embodiment, an equalizer includes a first signal path segment that includes a first plurality of serially connected transistors and current sources, a second signal path segment that includes a second plurality of serially connected transistors and current sources, and at least one termination resistor connected to the first and second signal path segments. The first plurality of serially connected transistors and current sources includes a first current source and a second current source connectable to a reference voltage and a first transistor and a second transistor connected between input terminals of the equalizer and the first and second current sources, where the first signal path segment further includes at least one resistor connected between the first and second current sources.

Two-dimensional high-speed equalizer with programmable direct current (DC) and peaking gains

One example discloses a level-shifter circuit, comprising: a pre-driver stage configured to receive differential inputs and generate differential pre-driver outputs; a first output stage coupled to receive the differential pre-driver outputs and generate a single-ended first stage output; a second output stage coupled to receive the differential pre-driver outputs and generate a single-ended second stage output; and wherein the first and second stage outputs together form a differential output.

Level-shifter

Various embodiments relate to a receiver, including: a first bias circuit configured to bias a first and second transistor based upon an bias enable signal and a receive enable signal; a first node between the first transistor and a third transistor; a second node between the second transistor and a fourth transistor; and a second bias circuit configured to bias the first node and the second node based upon the bias enable signal, wherein the third transistor is connected to a first differential output and the gate of the third transistor is connected to a first differential input, and wherein the fourth transistor is connected to a second differential output and the gate of the fourth transistor is connected to a second differential input.

Fast startup technique and circuit for a receiver

Various embodiments relate to a skew detector circuit, including: a logic circuit having two inputs configured to generate a logic 1 output when the two inputs have a logic 0 value and generator a logic 0 output when the two input have a logic 1 value; a first level shifter configured to increase the output of the logic circuit to a higher voltage; a second level shifter configured to increase the output of the first level shifter to a higher voltage; and a voltage regulator configured to produce a first voltage for the logic circuit, a second voltage for the first level shifter, and a third voltage for the second level shift.

Skew detection system and method to remove unwanted noise due to skewed signals

A circuit is disclosed. The circuit includes an input port, an output port, a squelch detector and a disconnect detector. The squelch detector and the disconnect detector are enabled or disabled by a signal such that only one of the squelch detector and the disconnect detector is active at a given time. When the squelch detector is active, a threshold generator generates a squelch threshold for the squelch detector based on a squelch configuration data indicative of a predefined squelch threshold. When the disconnect detector is active, the threshold generator generates a disconnect threshold for the disconnect detector based on a disconnect configuration data indicative of a predefined disconnect threshold.

Squelch and disconnect detector

A wideband buffer circuit and a wideband communication circuit that uses the wideband buffer circuit. The wideband buffer circuit includes first and second transistors deployed as a voltage buffer and connected to first and second input terminals, first and second parallel resistor-capacitor pairs connected to the first and second transistors, first and second cross-coupled transistors connected to the first and second parallel resistor-capacitor pairs and connected to first and second output terminals, and first and second current sources connected to the first and second cross-coupled transistors and a fixed voltage. The first transistor, the first parallel resistor-capacitor pair, the first cross-coupled transistor and the first current source are connected in series. The second transistor, the second parallel resistor-capacitor pair, the second cross-coupled transistor and the second current source are connected in series.

Wideband buffer with DC level shift and bandwidth extension for wired data communication

A continuous time linear equalization (CTLE) circuit is disclosed. The CTLE circuit includes a passive CTLE circuit and an active CTLE circuit. The active CTLE circuit includes a differential transistor pair and the output of the passive CTLE is configured to drive gates or bases of the differential transistor pair.

Continuous time linear equalization circuit

One example discloses a current monitoring device, including: a sense impedance configured to receive a current to be monitored; an impedance divider, coupled to the sense impedance, and configured to convert the current to be monitored to a differential voltage to be monitored; a reference circuit configured to generate a differential reference voltage; a comparator coupled to the impedance divider and the reference circuit and configured to output a signal if the differential voltage to be monitored is different than the differential reference voltage; and wherein the reference circuit includes a comparator trimming circuit configured to vary the differential reference voltage to compensate for offset biases in the comparator.

Current monitoring device

A continuous time linear equalization (CTLE) circuit is disclosed. The CTLE circuit includes an input port, an output port, a first differential transistor pair coupled to the input port and the output port and a second differential transistor pair. The CTLE circuit further includes a first degenerative impedance circuit coupled between the first differential transistor pair and ground. The first degenerative impedance includes switchable components to vary impedance of the first degenerative impedance circuit. The CTLE circuit also includes a second degenerative impedance circuit coupled between the second differential transistor pair and ground. The second degenerative impedance includes switchable components to vary impedance of the second degenerative impedance circuit, wherein the resistive part of the impedance of the first degenerative impedance circuit is equal to the impedance of the second degenerative impedance circuit.

Continuous time linear equalization circuit with programmable gains

A free running oscillator (FRO) includes a reference current generator, a current converter, and first and second oscillator cores. The reference current generator generates a first current. The current converter generates a second current based on the first current. The first oscillator core generates a clock signal at a first frequency based on a first value of the second current. The second oscillator core generates a clock signal at a second frequency based on a second value of the second current. The second frequency may be lower than the first frequency, and the second value of the second current lower than the first value of the second current.

High-accuracy dual-mode free running oscillator

Embodiments of redrivers and resistive units for redrivers are disclosed. In an embodiment, a resistive unit for a redriver includes at least one resistor connected to an input/output terminal of the redriver, at least one switch serially connected to the at least one resistor, and a voltage regulator connected to the at least one switch and configured to generate a termination voltage for the at least one switch. Instead of grounding the at least one resistor, using the voltage regulator can avoid large voltage jump at input/output terminals to keep connected devices safe.

Redriver and resistive unit for a redriver

A circuit for translating a voltage of a digital signal from a first voltage level of a first voltage domain to a second voltage level of a second voltage domain is disclosed. The circuit includes a configurable circuit to be coupled between the first voltage domain and the second voltage domain. The configurable circuit includes a plurality of parallel data paths, wherein the configurable circuit is configured to enable only one of the plurality of data paths at a given time. A first path in the plurality of parallel data paths is configured to be enabled when the first voltage level is greater than the second voltage level and a second path in the plurality of parallel data paths is configured to be enabled when the first voltage level is lesser than the second voltage level.

Circuit to support multiple voltage level input/output

One example discloses an interface circuit, including: an inductive coil having a first, second and third terminal; wherein the first terminal is coupled to an external interface port; wherein the second terminal is coupled to a first communication port; wherein the third terminal is coupled to a second communication port; and wherein the inductive coil is configured to attenuate an equivalent capacitance from at least one of the terminals.

Interface circuit

Embodiments of an oscillator and a method of operating an oscillator are disclosed. In an embodiment, an oscillator can include a ring oscillator core, a control circuit, and a timer that coordinates timing of the control circuit to avoid a current resulting from a voltage level associated with an output of the ring oscillator core during a startup and to allow the ring oscillator core to operate with a low startup current and a low operational power.

Growing community of inventors

Chandler, AZ, United States of America

Xu Zhang