Micron Technology Incorporated

Huawei Technologies Co., Limited

Alibaba Group Holding Limited

Wangsu Science & Technology Co., Ltd.

Shanghai Eastsoft Microelectronics Co., Ltd.

Chinese Academy of Sciences

Shanghai Jiaotong University

Hirschmann Car Communication Gmbh

Shanghai Investigation, Design & Research Institute Co., Ltd.

Xu Zhang

Xing Wang

Liang Wang

Xinghui Duan

Zhen Gu

Huachen Li

Jingjing Tao

Liping Xu

Ruijin Liu

Kishore Kumar Muchherla

Sampath K Ratnam

Ashutosh Malshe

Harish Reddy Singidi

Michael G Miller

Jie Yang

Zhong Xian Li

Bin Zhao

Jie Zhou

Eric Kwok Fung Yuen

Guanzhong Wang

Xiaowei Chen

Wei Li

Bin Wang

Jian Hui Huang

Guan Zhong Wang

Shuai Li

Zhixiong Yang

Kun Zhang

Haijie Gu

Xiaolai Zhu

Liping Zhao

Junjun Wang

Jinyun Wang

Sheng Yao

Wei Lei

Zhongning Chen

Guang Ning

Yue Jiang

Wen Yin

Xiaojun Zhang

Xiaoying Li

Yang Ye

Xiaoping Fan

Tian Liang

Yajuan Zheng

Zhonghua Deng

Jia Xu

Qing-Yan Liu

Zhihuai Pan

Peng-Song Wu

Yi-Huo Ye

Menghui Zhang

Shui Cao

Xin Yang

Xiaoyan Pang

Yifei Zhang

Liyi Zhang

Juan Jiang

Ke Fan

Li Ye

Shifang Luan

Lijun Peng

Hai Hao

Wenyu Li

Zhengbao Sun

Le Chen

Jialong Li

Jiandong Xiao

Liantao Jiang

Ran Yang

Yunguang Xun

Binggang Chen

Yufeng Zhao

Qiuyan Yan

Yuwei Li

Linghua Wang

Jiejie Lv

Shaoshun Li

Rubing Wang

Xiaogang Zheng

Louhua Zhu

Duoquan Li

Jiaxiang Xie

Lan Bao

Example error correction methods and apparatus are described. In one example method, a register controller detects an error existing in a memory, and after detecting an uncorrected error (UCE), obtains a memory address in which the UCE occurs. The register controller reads raw data from a location indicated by the memory address, stores preset first data in the location indicated by the memory address, and reads second data from the location after storing the first data in the location. The register controller compares the first data with the second data to determine a first failure location in the location, determines raw data stored in the first failure location from the raw data in the location, and performs error correction on the raw data stored in the first failure location.

Error correction method and apparatus

Methods, systems, and devices for mitigating memory die misalignment are described. A memory system may receive a command to write data to a memory device including a memory die. The memory system may determine whether the data indicated by the command (e.g., a first set of data) satisfies a threshold size. If the first set of data satisfies the threshold size, the memory system may determine whether data currently in a write buffer aligns with a boundary of the memory die. For example, depending on the data currently in the buffer, adding the first set of data to the buffer may result in die misalignment for the first set of data. To mitigate die misalignment, the memory system may pad data (e.g., add dummy data) to the write buffer, such that the padding aligns the data with the die boundary.

Techniques to mitigate memory die misalignment

Methods, systems, and devices for memory management procedures for write boost mode are described. A memory system may receive a command to write data. The memory system may write the data to a first location of the memory system using a first mode for storing one bit per memory cell based on receiving the command. The memory system may select a first portion of the data to rewrite to the memory system using a second mode for storing two or more bits per memory cell based on one or more parameters satisfying one or more thresholds. The memory system may write the first portion of the data to a second location of the memory system using the second mode based on selecting the first portion of the data. The memory system may maintain a second portion of the data at the first location of the memory system.

Memory management procedures for write boost mode

Techniques are described herein for performing a flush operation for a write booster buffer of a memory system. The flush operation may include swapping valid blocks in the write booster buffer for invalid blocks in a storage space of the memory system. After swapping the blocks, the memory system may transfer the information from a first type of blocks that were formerly assigned to the write booster buffer to a second type of blocks in the storage space. In such a flush operation, space is made available in the write booster buffer with less latency than it would take to transfer information between blocks, thereby improving the performance of the write booster mode.

Write booster buffer flush operation

The present disclosure provides a medical adhesive and a preparation method thereof, comprising a component A and a component B: the component A comprises a cycloketene acetal compound and an oxidizing agent; the component B comprises a vinyl monomer, a cross-linking agent and a reducing agent, wherein the cycloketene acetal compound is selected from one or more of 2-methylene-1,3-dioxepane, 2-methylene-4-phenyl-1,3-dioxolane, 5,6-benzo-2-methylene-1,3-dioxepane and 4,7-dimethyl-2-methylene-1,3-dioxepane. The medical adhesive overcomes the disadvantages of conventional medical adhesives.

Medical adhesive and preparation method thereof

A tool for an offshore wind power foundation pile includes a steel pipe pile, a pile core, a pile cap, and a pile shoe. A cutting shoe portion is arranged at a bottom of the steel pipe pile, and an outer diameter of the pile shoe is larger than an outer diameter of the cutting shoe portion; the pile cap is detachably connected to the top of the steel pipe pile; the pile core is located in the steel pipe pile, the pile core is detachably connected to the pile shoe, and a length of the pile core is larger than or equal to a length of the steel pipe pile; the pile cap is further provided with a pile core accommodating groove and a pile core limiting portion; the pile core limiting portion includes a pile core limiting block and a limiting hole.

Tool for offshore wind power foundation pile and method for using same

Methods, systems, and devices for validity mapping techniques are described. A memory device may use a change log to update a mapping that indicates whether data stored at respective physical addresses is valid. For example, the memory device may receive a command associated with data having a corresponding set of addresses (whether logical block addresses or physical addresses). The memory device may set an entry of the change log based on whether the set of addresses are consecutive. For example, the memory device may identify whether the set of addresses are consecutive and may set a flag in the entry of the change log to indicate whether the addresses are consecutive. Then, the memory device may update one or more entries of the mapping corresponding to the entry of the change log to indicate whether the addresses corresponding to the one or more entries of the mapping store valid data.

Validity mapping techniques

Methods, systems, and devices for unmap backlog in a memory system are described. A memory system may be configured to support receiving an unmap command from a host system and signaling, to the host system, an indication that the unmap command has been processed (e.g., handled, acknowledged). In response to the unmap command, the memory system may proceed with various unmap operations, which may include unmapping at least some of the associated addresses after indicating that the unmap command has been processed. For example, a memory system may implement an unmap backlog table to identify sections of addresses that are to be unmapped (e.g., after indicating that the unmap command has been processed). In some examples, the memory system may support various aspects of prioritization between unmap operations (e.g., background unmap operations) and other access operations such as read operations, write operations, or other access operations.

Unmap backlog in a memory system

Methods, systems, and devices for logical-to-physical (L2P) mapping compression techniques are described. A memory system may use an L2P mapping to map logical addresses to physical addresses of the memory system. The L2P mapping may be a hierarchical L2P mapping divided into multiple levels or subsets that are used to identify a physical address corresponding to a logical address. The memory system may write data to a set of physical addresses that are consecutively indexed and may set a flag in an entry of a second-level of the L2P mapping (e.g., of a three-level L2P mapping) to indicate that the entry is associated with a starting physical address of the consecutively indexed physical addresses. The memory system may subsequently read the data starting at the starting physical address based on the flag (e.g., bypassing reading an entry of a lowest-level of the L2P mapping to determine the physical address).

Logical-to-physical mapping compression techniques

This application relates to the field of electronic technologies, and provides a printed circuit board and a manufacturing method thereof, and an electronic device. The printed circuit board has target holes that penetrate through the printed circuit board, and an area that is not provided with the target holes has blocking structures (B) for blocking liquid flow, where the area is on at least one side that is of the printed circuit board and that is connected to the target holes.

Printed circuit board and manufacturing method thereof, and electronic device

A packet processing method and a related apparatus are provided. The method includes: obtaining a first packet including first indication information, wherein the first indication information is used to indicate a data flow corresponding to the first packet; determining a target flow entry in an integrated flow table based on the first indication information, wherein the integrated flow table includes at least one flow entry, each flow entry includes a unified match entry and a comprehensive behavior entry, the unified match entry uniquely identifies a data flow, a unified match entry of the target flow entry identifies the same data flow as indicated by the first indication information; and performing an operation on the first packet based on a comprehensive behavior entry included in the target flow entry.

Packet processing method and apparatus

Devices and techniques for data removal marking in a memory device are described herein. A delete command can be received at the memory device. A count of data portions in the delete command can be compared to determine whether the count is below a threshold. In response to determining that the count of data portions is below the threshold, the data portions can be written to a buffer. When a buffer full event is detected, a segment of an L2P data structure can be loaded into working memory of the memory device. Then, each record in the segment of the L2P data structure that has a corresponding entry in the buffer can be updated to mark the data as removable (e.g., invalid).

Data removal marking in a memory device

Disclosed in some examples are memory devices which feature intelligent adjustments to SLC cache configurations that balances memory cell lifetime with performance. The size of the SLC cache can be adjusted during usage of the memory device based upon a write amplification (WA) metric of the memory device. In some examples, the size of the SLC cache can be adjusted during usage of the memory device based upon a write amplification (WA) metric of the memory device and a memory device logical saturation metric (percentage of valid user data written in the device of the total user size).

SLC cache allocation

A packet processing method and device are provided, to save CPU resources consumed by parsing a packet. The method includes: parsing, by an intelligent network interface card, a received first packet to obtain an identifier of the first packet; updating, by the intelligent network interface card, a control field of a first memory buffer based on the identifier of the first packet; storing, by the intelligent network interface card, a payload of the first packet or a packet header and a payload of the first packet into the first address space through DMA based on an aggregation position of the first packet; aggregating, by a host, the first address information and at least one piece of second address information based on an updated control field in the first mbuf; and reading, by a virtual machine, address information, to obtain data in an address space indicated by the address information.

Packet processing method and related device

Growing community of inventors

Shanghai, China

Xu Zhang