Stats Chippac Pte. Ltd.

Xu Sheng Bao

Yaojian Lin

Kang Chen

Seng Guan Chow

Rui Huang

Ma Phoo Pwint Hlaing

Lee Sun Lim

A semiconductor device has a first conductive layer and a semiconductor die disposed adjacent to the first conductive layer. An encapsulant is deposited over the first conductive layer and semiconductor die. An insulating layer is formed over the encapsulant, semiconductor die, and first conductive layer. A second conductive layer is formed over the insulating layer. A first portion of the first conductive layer is electrically connected to Vand forms a ground plane. A second portion of the first conductive layer is electrically connected to Vand forms a power plane. The first conductive layer, insulating layer, and second conductive layer constitute a decoupling capacitor. A microstrip line including a trace of the second conductive layer is formed over the insulating layer and first conductive layer. The first conductive layer is provided on an embedded dummy die, interconnect unit, or modular PCB unit.

Semiconductor device having an embedded conductive layer for power/ground planes in Fo-eWLB

Semiconductor device and method of forming embedded conductive layer for power/ground planes in Fo-eWLB

A semiconductor device has a substrate containing a transparent or translucent material. A spacer is mounted to the substrate. A first semiconductor die has an active region and first conductive vias electrically connected to the active region. The active region can include a sensor responsive to light received through the substrate. The first die is mounted to the spacer with the active region positioned over an opening in the spacer and oriented toward the substrate. An encapsulant is deposited over the first die and substrate. An interconnect structure is formed over the encapsulant and first die. The interconnect structure is electrically connected through the first conductive vias to the active region. A second semiconductor die having second conductive vias can be mounted to the first die with the first conductive vias electrically connected to the second conductive vias.

Semiconductor device and method of forming EWLB semiconductor package with vertical interconnect structure and cavity region

A flip chip style semiconductor package has a substrate with a plurality of active devices formed thereon. A contact pad is formed on the substrate. An under bump metallization (UBM) layer is in electrical contact with the contact pad. A passivation layer is formed over the substrate. In one case, the UBM layer is disposed above the passivation layer. Alternatively, the passivation layer is disposed above the UBM layer. A portion of the passivation layer is removed to create a passivation island. The passivation island is centered with respect to the contact pad with its top surface devoid of the UBM layer. A solder bump is formed over the passivation island in electrical contact with the UBM layer. The passivation island forms a void in the solder bump for stress relief. The UBM layer may include a redistribution layer such that the passivation island is offset from the contact pad.

Semiconductor package with passivation island for reducing stress on solder bumps

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Xu Sheng Bao