International Business Machines Corporation

Globalfoundries Inc.

Xu Ouyang

Yunsheng Song

Louis C Hsu

Louis L Hsu

Chih-Chao Yang

Ping-Chuan Wang

Yongchun Xin

Tso-Hui Ting

Rajiv V Joshi

Oleg Gluschenkov

Lars W Liebmann

Keith Kwong Hon Wong

Louis Lu-Chen Hsu

Yun-Yu Wang

Fook-Luen Heng

Zhijian Yang

Geng Han

Haizhou Yin

Robert C Wong

Yuen H Chan

Xinhui Wang

Howard Hao Chen

James M Rice

Steven B Herschbein

Ishtiaq Ahsan

Stephen Wu

Rao H Desineni

George Y Gu

Ronald C Geiger, Jr

Hargurpreet Singh

Katherine V Hawkins

A test structure for an integrated circuit device includes a series inductor, capacitor, resistor (LCR) circuit having one or more inductor elements, with each inductor element having at least one unit comprising a first segment formed in a first metal layer, a second segment connecting the first metal layer to a semiconductor substrate beneath the first metal layer, and a third segment formed in the semiconductor substrate; and a capacitor element connected in series with each inductor element, the capacitor element defined by a transistor gate structure including a gate electrode as a first electrode, a gate dielectric layer, and the semiconductor substrate as a second electrode.

LCR test circuit structure for detecting metal gate defect conditions

A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage.

Modularized three-dimensional capacitor array

A flash memory structure having an enhanced capacitive coupling coefficient ratio (CCCR) may be fabricated in a self-aligned manner while using a semiconductor substrate that has an active region that is recessed within an aperture with respect to an isolation region that surrounds the active region. The flash memory structure includes a floating gate that does not rise above the isolation region, and that preferably consists of a single layer that has a U shape. The U shape facilitates the enhanced capacitive coupling coefficient ratio.

Flash memory structure with enhanced capacitive coupling coefficient ratio (CCCR) and method for fabrication thereof

An on-chip technique for noncontact electrical testing of a test structure on a chip is provided. On-chip photodiodes receives pump light from a pump light source, where the on-chip photodiodes are electrically connected to the test structure and are configured to generate power for the test structure. An on-chip coupling unit receives probe light from a probe light source, where the on-chip coupling unit is optically connected to on-chip waveguides through which the probe light is transferred. On-chip switches open in response to receiving voltage output from the test structure, and the on-chip switches remain closed when the voltage output is not received from the test structure. The on-chip switches pass the probe light when opened by the voltage output from the test structure. The on-chip switches block the probe light by remaining closed, when the voltage output is not received from the test structure.

Noncontact electrical testing with optical techniques

A system for performing alignment of two wafers is disclosed. The system comprises an optical coherence tomography system and a wafer alignment system. The wafer alignment system is configured and disposed to control the relative position of a first wafer and a second wafer. The optical coherence tomography system is configured and disposed to compute coordinate data for a plurality of alignment marks on the first wafer and second wafer, and send that coordinate data to the wafer alignment system.

Wafer alignment system with optical coherence tomography

A method for increasing overall yield in semiconductor manufacturing including routing wafers or wafer lots from tool to tool in a manner which at least partially neutralizes or compensates for processing variations. A system for increasing overall yield in semiconductor manufacturing includes a module for recording processing data from plural first and second types of tools and a module for routing wafers or wafer lots from tools of the first type of tools to tools of the second type of tools so as to at least partially neutralizes or compensate for processing variation.

Method for compensating for tool processing variation in the routing of wafers/lots

A method for laying out process dummy cells in relationship to inside memory cells of a memory array includes (a) calculating an initial process performance parameter for the memory array; (b) changing dummy cell layout configuration for a layer electrically connected to inside cells; (c) applying lithographic simulation and yield model for both the inside memory cells and the changed layout configuration process dummy cells; and (d) repeating steps (b) and (c) until yield is maximized. Checks may be performed to ensure that there is enough room to make the change and that there is no significant adverse effect to neighboring circuits. The process performance parameter may be yield or a process window for the inside memory cells.

Placement and optimization of process dummy cells

A static random access memory (SRAM) cell includes a first read port, the first read port having a first beta ratio; and a write port, the write port having a second beta ratio that is substantially lower than the first beta ratio. A static random access memory (SRAM) array includes a plurality of SRAM cells, an SRAM cell including a first read port, the first read port having a first beta ratio; and a write port, the write port having a second beta ratio that is substantially lower than the first beta ratio.

Dual beta ratio SRAM

A method of detecting low-probability defects in large transistor arrays (such as large arrays of SRAM cells), where the defects manifest themselves as asymmetrical leakage in a transistor (such as a pulldown nFET in an SRAM cell). These defects are detected by creating one or more test arrays, identical in all regards to the large transistor arrays up until the contact and metallization layers. Leakage is measured by applying an appropriate off-state voltage (e.g., 0V) by a common connection to all of the gates of the transistors in the test array, then measuring the aggregate drain/source leakage current, both forward and reverse (e.g., first grounded source and positively biased drain, then grounded drain and positively biased source) comparing the difference between the two leakage current measurements.

Detecting asymmetrical transistor leakage defects

A system and method for failure analysis of devices on a semiconductor wafer is disclosed. The present invention comprises the use of an inline focused ion beam milling tool to perform milling and image capturing of cross sections of a desired inspection point. The inspection points are located by identifying at least one fiducial that corresponds to an X-Y offset from the desired inspection point. The fiducials are recognized by a computer vision system. By automating the inspection process, the time required to perform the inspections is greatly reduced.

Inline low-damage automated failure analysis

A method of failure detection of an integrated circuit (IC) layout includes determining a critical path distance between a first geometric feature of the IC layout and a second geometric feature of the IC layout; and comparing the determined critical path distance to a defined minimum critical path distance between the first and second geometric features, wherein the defined minimum critical path distance corresponds to a desired electrical property of the IC layout, independent of any geometric-based ground rule minimum distance for the IC layout; identifying any determined critical path distances that are less than the defined minimum critical path distance as a design violation; and modifying the IC layout by eliminating the identified design violations.

Geometry based electrical hotspot detection in integrated circuit layouts

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Hopewell Junction, NY, United States of America

Xu Ouyang