United Microelectronics Corp.

Xu Ma

Hong Liao

Hong Ma

Bin Guo

Rui-Huang Cheng

Xiao-Fei Han

Xing-Hua Zhang

Yuan-Li Ding

Da-Jiang Yang

Chih-Ping Lee

A method for analyzing circuit pattern is disclosed. The method includes the steps of: providing a plurality of monitor metal line structures formed on discrete locations of a substrate corresponding to different values of variable factors; performing a defect review to identify failure locations of the monitor metal line structures; determining a failure tendency of the monitor metal line structures so as to determine a boundary of the variable factors; and determining whether adjustment is to be made to product metal line structures.

Method for analyzing circuit pattern

A test pattern structure including a first conductive layer and a second conductive layer is provided. The second conductive layer is directly disposed on the first conductive layer and connected to the first conductive layer through a plurality of connection interfaces. The test pattern structure of the present invention can detect the interconnection failure quickly and correctly without SEM identification.

Test pattern structure

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Xu Ma