Nxp Usa, Inc.

Freescale Semiconductor,inc.

Icemos Technology Corporation

Xu Cheng

Jiang-kai Zuo

Daniel J Blomberg

Zhihong Zhang

Xin Lin

Hongning Yang

Ronghua Zhu

Won Gi Min

Todd C Roggenbauer

Jan Claes

Yujing Wu

James Gordon Boyd

Todd Roggenbauer

Jiang-Kai Zuo

Jianhua He

In one embodiment, a semiconductor die includes a polycrystalline semiconductor resistor structure (poly resistor structure). The poly resistor structure includes a resistive path between a first terminal and a second terminal. The poly resistor structure includes a first region having a net first conductivity type dopant concentration located in the resistance path and a second region having a net second conductivity type dopant concentration located in the resistance path. A silicide structure is located on both a first portion of the first region and a first portion of the second region to electrically connect the first portion of the first region and the first portion of the second region. In some embodiments, poly resistor structures with different conductivity type regions can be connected together.

Polycrystalline semiconductor resistor

A device () includes a substrate (-) with an upper semiconductor layer, buried semiconductor layer, and a DTI structure (-) defining an active device region; a dummy LDMOS device () in the active device region which includes a grounded drain (D) in a drift region (), a source (S, S) in a body region () which extends to contact the buried semiconductor layer, a gate electrode (G-G) formed so that the source and at least part of the gate electrode are connected with the body implant region, and a buffering semiconductor layer portion () adjacent the DTI structure; and one or more active LDMOS devices () positioned in the active device region to be separated from the DTI structure by the dummy LDMOS device () which reduces an electric field across the sidewall insulator layer () in the DTI structure.

Apparatus for extension of operation voltage

A method for improving breakdown voltage of a Laterally Diffused Metal Oxide Semiconductor (LDMOS) includes biasing a first well of a Field Effect Transistor (FET) to a first voltage. The first well is laterally separated from a second well. An isolation ring is charged to a second voltage in response to the first voltage exceeding a breakdown voltage of a diode connected between the isolation ring and the first well. The isolation ring laterally surrounds the FET and contacts a buried layer (BL) extending below the first well and the second well. A substrate is biased to a third voltage being less than or equal to the first voltage. The substrate laterally extends below the BL and contacts the BL.

LDMOS with diode coupled isolation ring

A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate and defining a core device area within the doped isolation barrier, an isolation contact region disposed in the semiconductor substrate outside of the core device area and to which a voltage is applied during operation, and a depleted well region disposed in the semiconductor substrate outside of the core device area. The depleted well region electrically couples the isolation contact region and the doped isolation barrier such that the doped isolation barrier is biased at a voltage level lower than the voltage applied to the isolation contact region.

Partially biased isolation in semiconductor devices

Deep trench isolation structures and systems and methods including the same are disclosed herein. The systems include a semiconductor device. The semiconductor device includes a semiconductor body, a device region, and the deep trench isolation structure. The deep trench isolation structure is configured to electrically isolate the device region from other device regions that extend within the semiconductor body. The deep trench isolation structure includes an isolation trench, a dielectric material that extends within the isolation trench, a first semiconducting region, and a second semiconducting region. The methods include methods of operating an integrated circuit device that includes a plurality of semiconductor devices that include the disclosed deep trench isolation structures.

Deep trench isolation structures and systems and methods including the same

A device includes a semiconductor substrate, a buried doped isolation layer disposed in the semiconductor substrate to isolate the device, a drain region disposed in the semiconductor substrate and to which a voltage is applied during operation, and a depletion region disposed in the semiconductor substrate and having a conductivity type in common with the buried doped isolation barrier and the drain region. The depletion region reaches a depth in the semiconductor substrate to be in contact with the buried doped isolation layer. The depletion region establishes an electrical link between the buried doped isolation layer and the drain region such that the buried doped isolation layer is biased at a voltage level lower than the voltage applied to the drain region.

Partial, self-biased isolation in semiconductor devices

A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate and defining a core device area within the doped isolation barrier, an isolation contact region disposed in the semiconductor substrate outside of the core device area, and a body region disposed in the semiconductor substrate within the core device area, and in which a channel is formed during operation. The body region is electrically tied to the isolation contact region. The body region and the doped isolation barrier have a common conductivity type. The body region is electrically isolated from the doped isolation barrier within the core device area. The doped isolation barrier and the isolation contact region are not electrically tied to one another such that the doped isolation barrier is biased at a different voltage level than the isolation contact region.

A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate to isolate the device, a drain region disposed in the semiconductor substrate and to which a voltage is applied during operation, and a depleted well region disposed in the semiconductor substrate, and having a conductivity type in common with the doped isolation barrier and the drain region. The depleted well region is positioned between the doped isolation barrier and the drain region to electrically couple the doped isolation barrier and the drain region such that the doped isolation barrier is biased at a voltage level lower than the voltage applied to the drain region.

Self-adjusted isolation bias in semiconductor devices

An integrated semiconductor device includes a substrate of a first conductivity type, a buried layer located over the substrate, an isolated region located over a first portion of the buried layer, and an isolation trench located around the isolated region. A punch-through structure is located around at least a portion of the isolation trench. The punch-through structure includes a second portion of the buried layer, a first region located over the second portion of the buried layer, the first region having a second conductivity type, and a second region located over the first region, the second region having the first conductivity type.

Deep trench isolation

A capacitor suitable for inclusion in a semiconductor device includes a substrate, a first metallization level, a capacitor dielectric, a capacitor plate, an interlevel dielectric layer, and a second metallization level. The first metallization level overlies the substrate and includes a first metallization plate overlying a capacitor region of the substrate. The capacitor dielectric overlies the first metallization plate and includes a dielectric material such as a silicon oxide or silicon nitride compound. The capacitor plate is an electrically conductive structure that overlies the capacitor dielectric. The interlevel dielectric overlies the capacitor plate. The second metallization layer overlies the interlevel dielectric layer and may include a second metallization plate and a routing element. The routing element may be electrically connected to the capacitor plate. The metallization plates may include a fingered structure that includes a plurality of elongated elements extending from a cross bar.

Metal-insulator-metal capacitor

Deep trench isolation structures and systems and methods including the same are disclosed herein. The systems include a semiconductor device. The semiconductor device includes a semiconductor body, a device region, and the deep trench isolation structure. The deep trench isolation structure is configured to electrically isolate the device region from other device regions that extend within the semiconductor body. The deep trench isolation structure includes an isolation trench, a dielectric material that extends within the isolation trench, a first semiconducting region, and a second semiconducting region. The methods include methods of manufacturing a semiconductor device that includes the disclosed deep trench isolation structures. The methods also include methods of operating an integrated circuit device that includes a plurality of semiconductor devices that include the disclosed deep trench isolation structures.

A method of fabricating a transistor includes forming a field isolation region in a substrate. After forming the field isolation region, dopant is implanted in a first region of a substrate for formation of a drift region. A drain region is formed in a second region of the substrate. The first and second regions laterally overlap to define a conduction path for the transistor. The first region does not extend laterally across the second region.

Drain-end drift diminution in semiconductor devices

A superjunction semiconductor device is provided having at least one column of a first conductivity type and at least one column of a second conductivity type extending from a first main surface of a semiconductor substrate toward a second main surface of the semiconductor substrate opposed to the first main surface. The at least one column of the second conductivity type has a first sidewall surface proximate the at least one column of the first conductivity type and a second sidewall surface opposed to the first sidewall surface. A termination structure is proximate the second sidewall surface of the at least one column of the second conductivity type. The termination structure includes a layer of dielectric of an effective thickness and consumes about 0% of the surface area of the first main surface. Methods for manufacturing superjunction semiconductor devices and for preventing surface breakdown are also provided.

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Chandler, AZ, United States of America

Xu Cheng