Adeia Semiconductor Bonding Technologies Inc.

Adeia Semiconductor Inc.

Xu Chang

Belgacem Haba

Rajesh Katkar

Javier A DeLaCruz

Stephen L Morein

Liang Wang

Kenneth Duong

David Edward Fisch

Aspects of the disclosure relate to forming a completed stack of layers. Forming the completed stack of layers may include forming a first stack of layers on a first substrate and forming a second stack of layers on a second substrate. The first stack of layers may be bonded to the second stack of layers. The first or second substrate may be removed. Prior to bonding the first stack of layers and the second stack of layer, one or more holes may be etched in the first stack of layers. After removing the second substrate, one or more holes may be etched in the second stack of layers, wherein each of the one or more holes in the second stack of layers extend into a corresponding hole in the one or more holes in the first stack of layers.

3D NAND-high aspect ratio strings and channels

3D NAND—high aspect ratio strings and channels

Aspects of the disclosure relate to forming stacked NAND with multiple memory sections. Forming the stacked NAND with multiple memory sections may include forming a first memory section on a sacrificial substrate. A logic section may be formed on a substrate. The logic section may be bonded to the first memory section. The sacrificial substrate may be removed from the first memory section and a second memory section having a second sacrificial substrate may be formed and bonded to the first memory section.

Stacked architecture for three-dimensional NAND

3D NAND&#x2014;high aspect ratio strings and channels

A microelectronic circuit structure comprises a stack of bonded layers comprising a bottom layer and at least one upper layer. At least one of the upper layers comprises an oxide layer having a back surface and a front surface closer to the bottom layer than the back surface, and a plurality of FD-SOI transistors built on the front surface. At least a first back gate line and a second back gate line extend separate from each other above the back surface for independently providing a first back gate bias to a first group of transistors and a second back gate bias to a second different group of transistors.

Back biasing of FD-SOI circuit blocks

Growing community of inventors

San Jose, CA, United States of America

Xu Chang