Zipalog Inc.

Xiyuan Wu

Michael Krasnicki

Felicia James

A computer implemented method of translation of verification commands of an electronic design file of an electronic circuit defined by the electronic design file, comprising receiving, at a processor, the electronic design file defining a functional level electronic design of the electronic circuit, wherein said electronic circuit comprises at least two subsystems and said electronic circuit includes at least two configuration options for the at least two subsystems, receiving along with the electronic design file, at least one analog test harness model having at least one indirect branch contribution statement, translating said at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon said at least one analog test harness model and said electronic design file and generating a netlist for the electronic circuit based at least in part upon said translation of said at least one indirect branch contribution statement.

Computer implemented system and method of translation of verification commands of an electronic design

A computer implemented method of translation of verification commands of an electronic design, comprises the steps of receiving the electronic design, receiving at least one analog test harness model having at least one indirect branch contribution statement and having at least two stimulus parameter stored in at least one specification database and at least one measurement parameter stored in at least one specification database and at least one specification parameter stored in at least one specification database, a first stimulus parameter of the at least two stimulus parameters comprising an input to an input pin of the electronic circuit defined by the electronic design file, translating the at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon the at least one analog test harness model and at least one of at least two stimulus parameter stored in at least one specification database and at least one measurement parameter stored in at least one specification database and at least one specification parameter stored in at least one specification database and generating a netlist based at least in part upon the translation.

A computer implemented method of translation of verification commands of an electronic design, comprises the steps of receiving the electronic design, receiving at least one analog test harness model having at least one indirect branch contribution statement and having at least one of at least one stimulus parameter stored in at least one specification database and at least one measurement parameter stored in at least one specification database and at least one specification parameter stored in at least one specification database, translating the at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon the at least one analog test harness model and at least one of at least one stimulus parameter stored in at least one specification database and at least one measurement parameter stored in at least one specification database and at least one specification parameter stored in at least one specification database and generating a netlist based at least in part upon the translation.

A computer implemented method of translation of verification commands of an electronic design, comprises the steps of receiving the electronic design, receiving at least one analog test harness model having at least one indirect branch contribution statement, translating the at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon the at least one analog test harness model and generating a netlist based at least in part upon the translation.

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Allen, TX, United States of America

Xiyuan Wu