Intel Corporation

Xiuting C Man

Jeremy J Shrall

Stephen H Gunther

Avinash N Ananthakrishnan

Krishnakanth Venkata Sistla

Ankush Varma

Devadatta V Bodas

Hang T Nguyen

Eric J DeHaemer

Shaun M Conrad

Martin Rowland

Chris Poirier

Thi Dang

Krishna K Rangan

Cyprian W Woo

Michael N Derr

Dorit Shapira

Stanley Steve Kulick

Jay D Schwartz

Don Soltis

Deepak Ganapathy

Christopher P Mozak

Inder M Sodhi

Christopher E Cox

Justin J Song

Nagi Aboulenein

Philip R Lehwalder

Rebecca Z Loop

Amir Ali Radjai

Don C Soltis, Jr

Avinash N Ananthakrishan

Lawrence A Cooper

Jeffery L Krieger

In an embodiment, a processor includes at least one execution unit to execute instructions, and an interrupt generation unit. The interrupt generation unit may be to: receive a plurality of values indicating thermal status values for a memory unit at multiple points in time across a first time window; determine a running average value based on the plurality of values indicating thermal status values in the memory unit; and in response to a determination that the running average value has exceeded a high thermal status threshold value, generate a thermal interrupt indicating a high thermal status event in the processor. Other embodiments are described and claimed.

Generation of processor interrupts using averaged data

In an embodiment, a processor includes a first power rail, a first component coupled to the first power rail, and a compensation control unit. The compensation control unit is to: detect a request to change a voltage level of the first power rail by a first voltage change amount; in response to detecting the request, determine that the first voltage change amount exceeds a first threshold level associated with the first component; and in response to determining that the first voltage change amount exceeds the first threshold level, initiate a first compensation action prior to changing the voltage level of the first power rail. Other embodiments are described and claimed.

Compensation control for variable power rails

One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may store different, appropriate performance related information for different configurations and usage cases of the processor for a same performance state of the processor.

Mechanism to provide workload and configuration-aware deterministic performance for microprocessors

Methods, systems, and apparatuses relating to package on package memory refresh and self-refresh rate management are described. In one embodiment, an apparatus includes a processor die, a dynamic memory die mounted to and overlapping the processor die, a first thermal sensor of the processor die disposed adjacent to a first hot spot from a first type of workload and a second thermal sensor of the processor die disposed adjacent to a second hot spot from a second type of workload, and a hardware control circuit of the processor die to cause a refresh of a capacitor of the dynamic memory die when either of an output of the first thermal sensor exceeds a first threshold value and an output of the second thermal sensor exceeds a second threshold value.

Apparatuses, methods, and systems for package on package memory refresh and self-refresh rate management

Dynamic monitoring of current draw by a memory device or memory subsystem can enable a power management system to adjust a memory access performance parameter based on monitored power usage. The system can generate a power usage characterization for the memory device and/or memory subsystem based on monitoring current draw for a known pattern, and then subsequently use the power usage characterization to determine how to adjust the memory access performance parameter.

Dynamic power measurement and estimation to improve memory subsystem power performance

Power gating control architectures. A memory device having at least a memory array and input/output (I/O) lines terminated on the memory device with termination circuitry coupled to receive a termination supply voltage (V) with power gating circuitry to selectively gate the termination supply voltage in response to a power gating control signal (VttControl) is coupled with a processing core coupled with the memory device, the processing core to selectively assert and deassert the VttControl signal.

Power gating for termination power supplies

In an embodiment, a processor includes a first domain with at least one core to execute instructions and a second domain coupled to the first domain and including at least one non-core circuit. These domains can operate at independent frequencies, and a power control unit coupled to the domains may include a thermal logic to cause a reduction in a frequency of the first domain responsive to occurrence of a thermal event in the second domain. Other embodiments are described and claimed.

Performing cross-domain thermal control in a processor

An apparatus that includes a semiconductor chip having a processor and an on-die non-volatile storage resource is described. The on-die non volatile storage is to store different, appropriate performance related information for different configurations and/or usage cases of the processor for a same performance state of the processor.

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Beaverton, OR, United States of America

Xiuting C Man