Taiwan Semiconductor Manufacturing Comp. Ltd.

TSMC China Company Limited

TSMC Nanjing Company, Limited

Huawei Technologies Co., Limited

TSMC China Company, Limiied

XiuLi Yang

He-Zhou Wan

Ching-Wei Wu

Kuan Cheng

Ming-En Bu

Cheng Hung Lee

Mu-Jen Huang

Luping Kong

Hung-Jen Liao

Hau-Tai Shieh

Yi-Tzu Chen

Fu-An Wu

Liangbo Zhuang

Xiaoxiao Zheng

Yi Qiang Yu

Jie Cai

Mengxiang Xu

Zong-Liang Cao

Wenchao Hao

A latch circuit includes a latch clock generator configured to generate a latched clock signal based on a clock signal and a first enable signal, and an input latch coupled to the latch clock generator to receive the latched clock signal. The input latch is configured to generate a latched output signal based on the latched clock signal and an input signal. In response to the first enable signal having a disabling logic level, the latch clock generator is configured to set a logic level of the latched clock signal to a corresponding disabling logic level, regardless of the clock signal. The latch clock generator includes a first inverter configured to generate an inverted signal of the first enable signal, and a NAND gate coupled to the first inverter to receive the inverted signal of the first enable signal. The NAND gate is configured to generate the latched clock signal based on the clock signal and the inverted signal of the first enable signal.

Latch circuit, memory device and method

A memory circuit includes a NAND logic gate configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The memory circuit further includes a first N-type transistor coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The memory circuit further includes a second N-type transistor coupled to the first N-type transistor and a reference voltage supply, and configured to receive a first clock signal. The memory circuit further includes a first latch coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.

Memory circuit and method of operating the same

A circuit includes a plurality of registers, each register including SRAM cells, a read port configured to receive a read address, a write port configured to receive a write address, a selection circuit, a latch circuit, and a decoder coupled in series between the read and write ports and the plurality of registers, and a control circuit. Responsive to a clock signal and read and write enable signals, the control circuit causes the selection circuit, the latch circuit, and the decoder to select a first register of the plurality of registers in a read operation based on the read address, and select a second register of the plurality of registers in a write operation based on the write address.

Shared decoder circuit and method

A device includes a first virtual power line, a second virtual power line, a first delay circuit, and a first wakeup detector. The first virtual power line and the second virtual power line are coupled to a power supply correspondingly through a first group of transistor switches and a second group of transistor switches. The first delay circuit is coupled between gate terminals of the first group of transistor switches and gate terminals in the second group of transistor switches. The first wakeup detector is configured to generate a first trigger signal after receiving a signal from the first delay circuit.

System and method of power management in memory design

A memory circuit includes a NAND logic gate, a first N-type transistor, a second N-type transistor, a first inverter and a first latch. The NAND logic gate is configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The first N-type transistor is coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The second N-type transistor is coupled to the first N-type transistor and a reference voltage supply, and configured to receive a first clock signal. The first inverter is coupled to the NAND logic gate, and configured to output a data signal inverted from the first signal. The first latch is coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.

A circuit includes a selection circuit configured to receive a first address from a first port and a second address from a second port, a first latch circuit coupled to the selection circuit and configured to output each of the first address and the second address received from the selection circuit, a decoder, and a control circuit. The control circuit is configured to generate a plurality of signals configured to cause the decoder to decode each of the first address and the second address.

A latch circuit includes a latch clock generator configured to generate a latched clock signal based on a clock signal and a first enable signal, and an input latch coupled to the latch clock generator to receive the latched clock signal. The input latch is configured to generate a latched output signal based on the latched clock signal and an input signal. In response to the first enable signal having a disabling logic level, the latch clock generator is configured to set a logic level of the latched clock signal to a corresponding disabling logic level, regardless of the clock signal.

A circuit includes a selection circuit configured to receive a first address at a first input and a second address at a second input, pass the first address to an output when a select signal has a first logical state, and pass the second address to the output when the select signal has a second logical state different from the first logical state. The circuit also includes a decoder configured to decode the passed first address or second address.

In some embodiments, a circuit comprises a plurality of memory banks, a column line tracking loop and/or a row line tracking loop, and a tracking circuit. The plurality of memory banks are arranged in a plurality of rows and a plurality of columns of memory building blocks. The column line tracking loop traverses at least a portion of the plurality of rows. The row line tracking loop traverses at least a portion of the plurality of columns. The tracking circuit is configured to receive a first edge of a first signal, cause the first edge of a first signal to be propagated through the column line tracking loop and/or through the row line tracking loop and cause a second edge of the first signal when receiving the propagated first edge of the first signal. The first signal is associated with accessing of the plurality of memory banks.

Multi-bank memory with line tracking loop

In some embodiments, a time division multiplexing (TDM) circuit is configured to receive an external clock signal and generate an internal clock signal that has at least one pulse during a clock cycle of the external clock signal. An address selector is configured to select a current address before a first time within one of the at least one pulse, and select a next address starting from the first time to generate a selected address. An address storage element is configured to receive the selected address from the address selector and provide a passed through or stored address. The provided address is the current address substantially throughout the one of the at least one pulse. A single-port (SP) memory is configured to access at least one SP memory cell at the address provided by the address storage element in response to the internal clock signal.

Time division multiplexed multiport memory

Embodiments of the present invention relate to the field of communications, and provide a message transmitting method and device. The method includes: transmitting, by a user equipment UE, a radio resource control request to a base station, where the UE is in an enhanced uplink cell forward access channel CELL_FACH state and a system information block SIB5 includes an uplink interference value; when no radio resource control response message is received from the base station within a preset time and it is determined that the current number of times the radio resource control request is transmitted is smaller than a preset maximum number of transmissions, read an SIB7 periodically and obtain the uplink interference value; when determining, according to the uplink interference value, to transmit the radio resource control request message to the base station, transmit the radio resource control request message to the base station again.

Message transmitting method and device

A semiconductor chip comprises a word line configured to be driven by a word line driver. The semiconductor chip also comprises a plurality of bit lines. Each bit line of the plurality of bit lines is configured to transmit a signal to a respective bit line amplifier. The semiconductor device further comprises a plurality of memory cells. At least one memory cell of the plurality of memory cells is at an intersection of the word line and a bit line of the plurality of bit lines. The at least one memory cell of the plurality of memory cells is a type selected from at least two memory cell types based on a distance of the intersection from an end of the word line.

Semiconductor device with more than one type of memory cell

A boost system for dual-port SRAM includes a comparator and a boost circuit. The comparator is configured to compare a first row address of a first port and a second row address of a second port, and output a first enable signal. The boost circuit is configured to boost a voltage difference between a first voltage source and a second voltage source according to the first enable signal.

Boost system for dual-port SRAM

A semiconductor memory chip that has word lines driven by respective word line drivers and bit lines to carry signals to respective bit line amplifiers/drivers with memory cells at intersections of the word lines and bit lines memory cells. The semiconductor memory chip including various memory cell types, the type of memory cell at an intersection based on a position of the intersection among the word lines and bit lines.

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Shanghai, China

XiuLi Yang