Cadence Design Systems, Inc.

Agilent Technologies, Inc.

Magma Design Automation, Inc.

Xisheng Zhang

Zhihong Liu

Hancheng Liang

Jianhe Guo

Pengfei Zhang

James Chieh-Tsung Chen

Jushan Xie

Jingkun Fang

Yuping Wu

Xucheng Pang

In an example embodiment, the system receives user inputs including: (1) a netlist that describes the circuit elements and connections of an integrated circuit; (2) a mathematical device model that corresponds to the integrated circuit and that includes an equation with a number of parameters and decision variables grouped into terms; and (3) a description of an input voltage. Based on these inputs, the system calculates an output such as a voltage or current. The system displays a GUI that includes a view which shows each of the terms of the equation after a value has been assigned to each parameter and to each decision variable and a view which shows each of the terms of the equation after reduction of the values assigned to each parameter and each decision variable. Upon receipt of a user's change to the value of a parameter, the system promptly updates the views.

Graphical user interface for viewing intermediate calculations from a device model

The present invention presents methods for modeling the high frequency and noise characterization of MOSFETs. The models may be readily implemented as part of a SPICE or other simulation in a design flow. In particular, this invention is capable of providing a sub-circuit representation of a MOSFET that can accurately predicate a MOSFET's low frequency, high frequency, and noise characterizations. An interface is described through which a user may simultaneously optimize all of these characterizations. Further, methods are presented for building models that can predicate the variations in MOSFETs due to manufacturing processes and generate a corresponding corner model.

MOSFET modeling for IC design accurate for high frequencies

A method for generating a layout for an analog circuit design is provided. The method includes tracing a signal flow through a circuit netlist, and partitioning the circuit netlist into a digital portion and an analog portion. A signal flow is defined through the analog portion of the circuit netlist. A system for generating a layout for an analog circuit design is also included.

Signal flow driven circuit analysis and partitioning technique

An exemplary method for simulating the effect of mismatch in design flows comprises receiving measured data, receiving an original model, extracting a mismatch model based on the measured data and the original model, attaching the mismatch model to the netlist to obtain a modified netlist, and simulating an effect of mismatch based on the modified netlist. In one embodiment, the extracting of a mismatch model includes selecting a set of model parameters, generating a distribution of mismatch values for each of the model parameters, extracting a set of linking coefficients based on said mismatch values, and extracting said mismatch model based on said set of linking coefficients. In another embodiment, the attaching of the mismatch model to the netlist includes determining a number of layers in the netlist, generating a copy of a lower layer in the netlist, the copy including a reference to a mismatch model definition, generating a copy of a higher layer in the netlist, replacing a reference to the lower layer in the higher layer by a reference to the copy of the lower layer, and generating a new model definition.

Apparatus and methods for modeling and simulating the effect of mismatch in design flows of integrated circuits

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Sunnyvale, CA, United States of America

Xisheng Zhang