Broadcom Corporation

Case Western Reserve University

Xinyu Yu

Sumant Ranganathan

Tom W Kwan

Steven L Garverick

Michael Inerfield

Jeyhan Karaoguz

Robert G Lorenz

Xicheng Jiang

David A Sobel

Sriraman Dakshinamurthy

Yee Ling Cheung

Jason C Hu

Fang Lin

Monika Gupta

Qiang Fu

Guowen Wei

Lemi Toygur

Yunli He

Bob Lukas

Jing Yang

A CT-SDADC of the present disclosure converts the analog input signal from a representation in an analog signal domain to a representation in a digital signal domain to provide the digital output signal. The CT-SDADC achieves the analog-to-digital conversion and ELDC by switching between two phases in the SAR sub-ADC: a sampling phase and a conversion phase. During the sampling phase, the SAR sub-ADC captures the analog input signal across multiple arrays of switchable capacitors. The conversion phase comprises a number of steps, and one or more bits of the digital output signal are resolved at each step of the conversion phase. A portion of the SC-DAC is driven by the delayed CT-SDADC output during the conversion phase to effectively compensate for excess loop delay caused by the CT-SDADC feedback loop.

Method and apparatus for excess loop delay compensation in continuous-time sigma-delta analog-to-digital converters

A CMOS analog and audio front-end circuit includes an enhanced analog-to-digital converter (ADC) that achieves a desired signal-to-noise-and-distortion (SNDR) and an analog-front-end transmit (TX) digital-to-analog converter (DAC). The enhanced ADC includes an improved single Op-Amp resonator coupled to a feed-forward loop and can substantially reduce signal transfer function (STF) peaking of the enhanced ADC. The CMOS analog and audio front-end circuit is integrated with a baseband processor.

Analog and audio mixed-signal front end for 4G/LTE cellular system-on-chip

Embodiments provide systems and methods for aligning the supply voltage signal applied to a power amplifier (PA) with the radio frequency (RF) output signal of the PA in a wireless device. The RF output signal is generated by applying a transmit signal to a transmit path of the wireless device. The supply voltage is generated by applying an envelope tracking (ET) signal, based on the transmit signal, to an envelope tracking (ET) path of the wireless device. Embodiments operate by estimating the delays of the ET path and the transmit path, and then controlling a relative delay between the transmit signal and the ET signal accordingly. In an embodiment, estimation of the delays of the ET path and the transmit path is done by correlating respective signals of each path.

Method of calibrating the delay of an envelope tracking signal

Operating a game controller to identify a user by receiving touch pad input from at least one touch sensitive pad of the game controller that has a plurality of touch sensitive elements. The touch pad input corresponds to the user's touch of at least some of the plurality of touch sensitive elements. The touch pad input is at least partially processed by processing circuitry of the game controller and transmitted to a game console via a communications interface of the game controller for processing of the at least partially processed touch pad input to identify the user via pattern recognition. At least partially processing the touch pad input can be by identifying at least one finger orientation, at least one finger spacing, at least one finger width, a plurality of finger knuckle/joint locations, and/or a plurality of finger lengths based upon the touch pad input.

Hand-held gaming device that identifies user based upon input from touch sensitive panel

An analog-to-digital converter (ADC) includes reference charge cancellation features to at least partially offset a voltage distortion on a bypass capacitor of a reference buffer due to a voltage reference hit taken by a switched capacitor bank with which the bypass capacitor is connected. The charge cancellation may be configured in logic to be input signal dependent because different resolved bits or transitions between resolved bits may cause different amounts of voltage reference hits. By adjusting the bypass capacitor in response to each of at least some of the reference hits while resolving a word of bits, the reference voltage signal provided by the bypass capacitor undergoes far less settling, remaining more stable and linear for a more accurate reference voltage. Furthermore, a smaller capacitor may be used for the bypass capacitor, reducing power consumption and area on chip.

Reference charge cancellation for analog-to-digital converters

An amplifier system can include an input amplifier configured to receive an analog input signal and provide an amplified signal corresponding to the analog input signal. A tracking loop is configured to employ delta modulation for tracking the amplified signal, the tracking loop providing a corresponding output signal. A biasing circuit is configured to adjust a bias current to maintain stable transconductance over temperature variations, the biasing circuit providing at least one bias signal for biasing at least one of the input amplifier and the tracking loop, whereby the circuitry receiving the at least one bias signal exhibits stable performance over the temperature variations. In another embodiment the biasing circuit can be utilized in other applications.

System and circuitry to provide stable transconductance for biasing

The present invention relates generally to analog-to-digital converters (ADCs). Embodiments of the present invention provide novel ADC architectures directed at reducing the overall ADC area and power consumption. Embodiments of the present invention may be used in pipelined ADCs, cyclic ADCs, and successive approximation (SAR) ADCs, for example. Further, embodiments of the present invention may be implemented using both single-ended and differential configurations.

Area-efficient analog-to-digital converter

Reliable and efficient sensing becomes increasingly difficult in harsher environments. A sensing module for high-temperature conditions utilizes a digital, rather than analog, implementation on a wireless platform to achieve good quality data transmission. The module comprises a sensor, integrated circuit, and antenna. The integrated circuit includes an amplifier, A/D converter, decimation filter, and digital transmitter. To operate, an analog signal is received by the sensor, amplified by the amplifier, converted into a digital signal by the A/D converter, filtered by the decimation filter to address the quantization error, and output in digital format by the digital transmitter and antenna.

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San Jose, CA, United States of America

Xinyu Yu