Shenzhen Corerain Technologies Co., Ltd.

Xinyu Niu

Kuen Hung Tsoi

Chao Xiong

Chenglong Zeng

Yuanchao Li

Jiadong Wang

Kai Ma

Li Jiao

Kuenhung Tsoi

Chenchen Lu

The present disclosure provides storage and accessing methods for parameters in a streaming AI accelerator chip, and relates to the technical field of artificial intelligence, wherein the streaming-based data buffer comprises: a plurality of banks, different banks being configured to store different data; a data read circuit configured to receive a read control signal and a read address corresponding to a computation task, in the case the read control signal corresponds to a first read mode, determine n banks from the plurality of banks based on the read control signal, and read first data required for performing the computation task in parallel from the n banks based on the read address, the first data comprising n pieces of data corresponding to the n banks in a one-to-one correspondence, n≥2, n being a positive integer.

Storage and accessing methods for parameters in streaming AI accelerator chip

A data stream architecture-based accelerator includes a storage unit, a read-write address generation unit and a computing unit. The storage unit includes a plurality of banks. The read-write address generation unit is used for generating storage unit read-write addresses according to a preset read-write parallelism, determining target banks in the storage unit according to the storage unit read-write addresses and reading to-be-processed data from the target banks for operations in the computing unit. The computing unit includes a plurality of data paths and is configured to determine target data paths according to a preset computing parallelism so that the target data paths can perform operations on the to-be-processed data to obtain processed data, and then store the processed data into the target banks according to the storage unit read-write addresses.

Data stream architecture-based accelerator, and data access method and device for accelerator

A sparse data storage method for deep learning, a computer device and a storage medium. The method includes: obtaining an offset between current non-zero data and previous non-zero data of the current non-zero data, and generating to-be-transmitted data according to the current non-zero data and the offset, where the to-be-transmitted data is stored in a first memory; obtaining the to-be-transmitted data, calculating an address increment according to the offset, and obtaining, according to the address increment, a storage address in which the current non-zero data is to be stored in a second memory; and transmitting the current non-zero data to the second memory, and storing the current non-zero data in the storage address in the second memory. According to the embodiments, the power consumption and costs required by deep learning operations can be reduced.

Sparse data storage method for deep learning, computer device and storage medium

Provided are a scheduling method and apparatus based on a deep learning node computation, and a storage medium. The scheduling method includes: a to-be-computed node of a preset neural network computation graph is acquired; a node type of the to-be-computed node is determined, where the node type includes a hardware computation node and a software computation node; in a case where the node type is the hardware computation node, the hardware computation node is scheduled to a first queue, and whether a hardware computing power module corresponding to the hardware computation node is occupied or not is determined; and in a case where the hardware computing power module is not occupied, the hardware computation node is input into the hardware computing power module for computing.

Scheduling method and device based on deep learning node computation, and storage medium

The present disclosure provides an artificial intelligence chip, an accelerator and an operation method, relating to the technical field of artificial intelligence, the chip comprising: a first operation circuit configured to execute a first operation to output a first operation result; a second operation circuit connected in parallel with the first operation circuit and configured to execute a second operation identical to the first operation to output a second operation result; and a third operation circuit configured to, upon receiving the first operation result and the second operation result, execute a third operation different from the first operation on the first operation result and the second operation result, respectively, to output a third operation result, respectively.

Artificial intelligence chip, accelerator and operation method

The embodiments of the present application provide a data processing method and apparatus of an AI chip and a computer device. The data processing method of the AI chip includes: determining a target AI model for processing data to be processed; matching, in the AI chip, a data flow network corresponding to the target AI model and a data flow direction of the data flow network; and processing the data to be processed based on the data flow network and the data flow direction.

Data processing method and apparatus of AI chip and computer device

A data flow-based neural network multi-engine synchronous calculation system, include: a plurality of calculation engines each including a plurality of calculation modules and at least one cache module located at different layers, and each calculation module is configured to calculate an input calculation graph provided by the cache module or the calculation module of a previous layer of a layer where each calculation module is located, so as to obtain an output calculation graph; and at least one synchronization module each being configured to monitor the data amount of the input calculation graph stored by the cache module on the same layer in each calculation engine, and control, when the data amount reaches a preset value corresponding to each cache module, each cache module on the same layer to output the stored input calculation graph to the calculation module on a next layer.

Data flow-based neural network multi-engine synchronous calculation system

Embodiments of the present disclosure provide an artificial intelligence (AI) chip and an AI chip-based data processing method. The AI chip includes: a data flow network for processing, on the basis of an AI algorithm, data to be processed. The data flow network includes: at least one calculation module, each configured to calculate, on the basis of one of at least one operation node corresponding to the AI algorithm, the data to be processed, and output a calculation result; and a next transfer module corresponding to each calculation module, connected to each calculation module, and configured to receive the calculation result output by each calculation module and process the calculation result, the data to be processed flowing in the data flow network according to a preset data flow direction.

Artificial intelligence chip and artificial intelligence chip-based data processing method

A data compression, decompression method, and an electronic device. The method includes the following steps: establishing an initial lookup table by using data with the same value in dataset to be compressed as one index, sequentially building a new Huffman tree corresponding to each index, and then adding a separator to obtain an encoding list containing a target encoding value and length, adding the encoding list to the initial lookup table to obtain a target lookup table. According to a separator of bitstream data, and searching the target lookup table in parallel, and use the indexes to obtain the decompression result of the data to be decompressed. Embodiments can perform a parallel decompression operation to increase a decompression speed, so that the decompression speed can meet the requirement of an AI engine for a large amount of weight data bandwidth in real time.

Data compression method, data decompression method, and electronic device

A data flow control device in a streaming architecture chip includes at least one first data buffer module, at least one operation module and at least one second data buffer module. The second data buffer module is configured to send a flow control count signal to the first data buffer module, the flow control count signal being used for informing the first data buffer module of an amount of data that can be received of the second data buffer module. The first data buffer module is configured to send a data signal and a valid signal to the second data buffer module via the operation modules according to the flow control count signal, the valid signal being used for indicating that a corresponding data signal is valid.

Data flow control device in streaming architecture chip

A neural network model conversion method, a server, and a storage medium are provided according to embodiments of the present disclosure. The neural network model conversion method includes: parsing a neural network model to obtain initial model information; reconstructing the initial model information to obtain streaming model information; generating a target model information file according to the streaming model information; and running, under a streaming architecture, the neural network model according to the target model information file.

Neural network model conversion method server, and storage medium

Provided is a data processing system. The system includes a data source, a data receiver, a plurality of source code data frame buffer regions, a data processing module and a state register. The data source is configured to generate a data frame, the data receiver is configured to receive the data frame, and write the data frame into one of a plurality of data frame buffer regions, each of the plurality of source code data frame buffer regions is configured to store a data frame to be processed, the data processing module is configured to perform subsequent processing on data and the state register is configured to store a state of the system and states of the plurality of source code data frame buffer regions.

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Shenzhen, China

Xinyu Niu