Huawei Technologies Co., Limited

Hangzhou H3c Technologies Co., Ltd

Huawei Techonlogies Co., Ltd.

Xinyu Hou

Sheng Chang

Haitao Guo

Haibin Wang

Chenghong He

Jiangen Liu

Rongyu Yang

Weibin Lin

Jie Zhang

Jin Zhaohu

Qiang Liu

Tianxiang Chen

Qun Jia

Guang Lu

An artificial intelligence (AI) switch chip includes a first AI interface, a first network interface, and a controller. The first AI interface is used by the AI switch chip to couple to a first AI chip in a first server. The first network interface is used by the AI switch chip to couple to a second server. The controller receives, through the first AI interface, data from the first AI chip, and then sends the data to the second server through the first network interface. By using the AI switch chip, when a server needs to send data in an AI chip to another server, an AI interface may be used to directly receive the data from the AI chip, and then the data is sent to the other server through one or more network interfaces coupled to the controller.

Transmission device and communication system for artificial intelligence chips

A data processing method comprising: After receiving an iPeripheral Component Interconnect Express (PCIe) packet, a network interface card stores a jinstruction segment in a jstorage unit that is in a first storage area. When all n instruction segments of a first send queue entry (SQE) are stored in the first storage area, the network interface card obtains the first SQE, an identifier of a queue pair (QP) to which the first SQE belongs, and a location identifier of the first SQE in the QP according to the instructions in n storage units in the first storage area; the network interface card performs data processing based on the identifier of the QP to which the first SQE belongs and the location identifier of the first SQE in the QP.

Data processing method, network interface card, and server

A computer subsystem and a computer system, where the computer subsystem includes L composite nodes (CNs), each CN includes M basic nodes, each basic node includes N central processing units (CPUs) and one node controller (NC). Any two CPUs in each basic node are interconnected. Each CPU in each basic node is connected to the NC in the basic node. The NC in each basic node has a routing function. Any two NCs in the M basic nodes are interconnected. A connection between the L CNs formed through connections between NCs enables communication between any two NCs to be no more than three hops. Hence, the computer subsystem and the computer system can reduce the kinds and the number of interconnection chips, and simplify an interconnection structure of a system, thereby improving reliability of the system.

Computer subsystem and computer system with composite nodes in an interconnection structure

According to a storage system, method, and apparatus for processing an operation request provided by embodiments of the present invention, a controller directly encapsulates a SCSI protocol operation request into an Ethernet operation request packet at the MAC layer instead of using the TCP/IP protocol layer and a disk enclosure decapsulates the Ethernet operation request to obtain the SCSI protocol operation request and sends the SCSI protocol operation request to a target disk, thereby reducing layers of encapsulation, reducing a processing delay of the storage system, and improving performance of the storage system.

Storage system, method, and apparatus for processing operation request

Storage system, method, and apparatus for processing multi-layer protocol encapsulation or decapsulation operation requests

The present invention provides a computer subsystem and a computer system. The computer subsystem includes L composite nodes, each composite node includes M basic nodes, each basic node includes N central processing units (CPUs) and one node controller. Any two CPUs in each basic node are interconnected. Each CPU in each basic node is connected to the node controller in the basic node. The node controller in each basic node has a routing function. Any two node controllers in the M basic nodes are interconnected. A connection between the L composite nodes formed through connections between node controllers enables communication between any two node controllers to be no more than three hops. The computer subsystem and the computer system according to embodiments of the present invention can reduce the kinds and the number of interconnection chips, and simplify an interconnection structure of a system, thereby improving reliability of the system.

The present invention provides a computer subsystem and a computer system. The computer subsystem includes L composite nodes, each composite node includes M basic nodes, each basic node includes N central processing units CPUs and one node controller NC, where any two CPUs in each basic node are interconnected, each CPU in each basic node is connected to the NC in the basic node, the NC in each basic node has a routing function, any two NCs in the M basic nodes are interconnected, and a connection between the L composite nodes formed through a connection between NCs enable communication between any two NCs to require at most three hops. The computer subsystem and the computer system according to embodiments of the present invention can reduce the kinds and the number of interconnection chips, and simplify an interconnection structure of a system, thereby improving reliability of the system.

A data transmission method, device and system to improve reliability of a data link. When the sender side detects erroneous data, the erroneous data is discarded and a data retransmission request is sent to the sender side to ensure correctness of received data and improve reliability of the data link; and, when the sender side detects the erroneous data and a bit error rate is greater than a preset bit error rate threshold, the data link gets into auto recovery, and data transmission is resumed after the recovery succeeds, thereby avoiding an excessively high bit error rate, preventing an excessively high probability of omitted checks (the higher the bit error rate is, the higher probability of omitted checks is), and further improving reliability of the data link.

Data transmission method, device and system

The present disclosure provides a CPU interconnect device, the CPU interconnect device connects with a first CPU, which includes a quick path interconnect QPI interface and a serial deserial SerDes interface, the quick path interconnect QPI interface receives serial QPI data sent from a CPU, converts the received serial QPI data into a parallel QPI data, and outputs the parallel QPI data to the serial deserial SerDes interface; the serial deserial SerDes interface converts the parallel QPI data output by the QPI interface into a high-speed serial SerDes data and then send the high-speed serial SerDes data to another CPU interconnect device connected with another CPU. The defects of poor scalability, long data transmission delay, and a high cost of an existing interconnect system among CPUs can be solved.

CPU interconnect device

A system for implementing interconnection fault tolerance between CPUs, a first CPU and a second CPU implements interconnection through a first CPU interconnect device and a second CPU interconnect device. The system adds a data channel between a first SerDes interface of the first CPU interconnect device and a second SerDes interface of the second CPU interconnect device, and transmits link connection state information and a link control signal through the added data channel. The system monitors a link state of any one link in a CPU interconnection system, transmits the link state through the added data channel, recovers any one of the connection links when determining whether any one of the first connection link, the second connection link and the third connection link is faulty.

Method and system for implementing interconnection fault tolerance between CPU

The present invention relates to a method for data output control, which comprises: obtaining the length of idle bits in the cache queue of a data output interface, and if the idle-bit length is equal to or longer than the length of the data to be sent on the interface, putting the data into the cache queue of the interface. In addition, this present invention discloses another data output control method, and two types of data output control apparatuses. Using this invention can avoid flow interruption.

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Hangzhou, China

Xinyu Hou