Qualcomm Incorporated

Xinwei Wang

Xiangdong Zhang

Yan Kit Gary Hau

Jing-Hwa Chen

Marc Gerald Dicicco

Zhenying Luo

Jisun Ryu

Yanjie Sun

James Francis Imbornone

ZhenQi Chen

Guoqing Fu

Chenliang Du

Tianzuo Xi

Haichuan Kang

Ashwin Duggal

Kihun Chang

Junzhi Yu

Frederic Carrez

Yongrong Zuo

An amplifier circuit includes an amplifier configured to receive a radio frequency (RF) input signal from an input node, a bias circuit comprising a reference transistor coupled between a reference current source and ground, and a bias transistor coupled to the reference transistor and configured to generate a main bias current to bias the amplifier, an input power sense circuit coupled to the input node, and an additional transistor coupled to the input power sense circuit and to the bias transistor, the additional transistor configured to generate an additional bias current to bias the amplifier, the additional bias current responsive to a power level of the RF input signal.

Radio frequency (RF) amplifier bias circuit

Certain aspects of the present disclosure are directed to an amplifier. The amplifier may include a transistor coupled to an output of the amplifier, and a resonator coupled between the output of the amplifier and a reference potential node, a resonant frequency of the resonator being set to be at a subharmonic of a fundamental frequency of the amplifier, and an impedance of the resonator being greater than a load impedance of the amplifier at the fundamental frequency of the amplifier.

Stability improvement circuit for radio frequency (RF) power amplifiers

Certain aspects of the present disclosure provide methods and apparatus for current-limiting protection of an amplifier, such as a power amplifier in a radio frequency (RF) front-end. One example current-limiting circuit generally includes a node coupled to a current source, a plurality of current-sinking devices coupled to the node, one or more switches coupled between the node and at least one of the plurality of current-sinking devices, and a bias circuit having an input coupled to the node and an output for coupling to an input of the amplifier.

Current-limiting circuit for a power amplifier

Exemplary embodiments are related to switch linearizer. A device may include at least one switch. The device may further include a linearizer coupled to the at least one switch and configured to cancel at least a portion of distortion generated by the at least one switch in an off-state.

Switch linearizer

A circuit including a radio frequency (RF) amplifier including a transistor configured to receive an RF signal at its control terminal, a capacitor coupled to a first terminal of the transistor, an inductor coupled to a second terminal of the transistor, wherein the capacitor and inductor form a loop from the first terminal to the second terminal, wherein the loop bypasses a parasitic inductance between the second terminal and ground.

Systems and methods providing a matching circuit that bypasses a parasitic impedance

Certain aspects of the present disclosure provide methods and apparatus for operating a power amplifier. In one example, the apparatus includes a power amplifier configured to amplify an input signal having a frequency to produce a radio frequency (RF) output signal at an output and a harmonic tuning circuit coupled between a power supply and the power amplifier output, the harmonic tuning circuit configured to reduce a current or voltage provided to the power amplifier via a resonance at one or more harmonics of the frequency of the input signal.

Methods and apparatuses for ruggedizing a power amplifier against breakdown using harmonic tuning

A step attenuator with constant input capacitance and having good performance is disclosed. In an exemplary design, an apparatus includes a step attenuator having a constant input capacitance for different amounts of attenuation. The step attenuator receives an input signal, provides a variable amount of attenuation for the input signal, and provides an output signal. The step attenuator may include a plurality of attenuator sections coupled in series. Each attenuator section may include a plurality of capacitors and may have the constant input capacitance. At least one of the plurality of attenuator sections may be selected or unselected to obtain a selected amount of attenuation for the step attenuator. An attenuator section may provide a predetermined amount of attenuation or a variable amount of attenuation when selected. The apparatus may further include a power detector that receives and determines the power of the output signal from the step attenuator.

Step attenuator with constant input capacitance

A device includes a first circuit path coupled to a first node and a second node, the first circuit path having at least one first varactor circuit configured to receive a first tuning voltage, the first circuit path having a resistor with a selectable value, and a second circuit path coupled to the first node and the second node, the second circuit path having at least one second varactor circuit configured to receive a second tuning voltage, the second circuit path having a capacitor with a selectable value.

Quadrature current-combining linearizing circuit for generating arbitrary phase and amplitude

Techniques for improving the linearity of radio-frequency (RF) front-end switches. In an aspect, open-loop techniques are disclosed for superimposing the output voltage of one or more negative rectifiers on a negative substrate bias voltage to reduce the non-linearities associated with voltage-dependent substrate leakage current. In another aspect, closed-loop techniques are further disclosed for maintaining the substrate bias voltage close to a reference voltage. Exemplary embodiments of the circuit blocks are further described.

Analog switch for RF front end

Power detectors with temperature compensation and having improved accuracy over temperature are disclosed. In an aspect of the disclosure, variations of a power detector gain over temperature is reduced by varying both the gate and drain voltages of MOS transistors within a power detector. In an exemplary design, an apparatus includes at least one MOS transistor, which receives an input signal, detects the power of the input signal based on a power detection gain, and provides an output signal indicative of the power of the input signal. The at least one MOS transistor is applied a variable gate bias voltage and a variable drain bias voltage in order to reduce variations of the power detection gain over temperature. At least one additional MOS transistor may receive a second variable gate bias voltage and provide the variable drain bias voltage for the at least one MOS transistor.

Power detector with temperature compensation

An amplified stepped gain mixer portion improves the signal-to-noise ratio of a receiver by using multiple gain states to improve linearity. The mixer portion includes an amplifier, a switch and two transistors. The amplifier output is coupled to the sources of the two transistors. An oscillating signal is present on the transistor gates. The transistor drains are coupled to one another through the switch when the switch is closed. The mixer portion operates in two modes. In a 1/2 mode, the mixer portion output current flows only through the first transistor and not through the second transistor because the switch is open. In a 2/2 mode, the mixer portion output current flows through both transistors. The mixer portion is configured such that the switch is closed when a switching signal is asserted. The switching signal is asserted when a bit of a mixer control register is written to.

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Dunstable, MA, United States of America

Xinwei Wang