Globalfoundries Singapore Pte. Ltd.

Globalfoudnries Singapore Pte. Ltd.

Xinshu Cai

Shyue Seng Tan

Eng Huat Toh

Kiok Boone Elgin Quek

Yongshun Sun

Danny Pak-Chum Shum

Lanxiang Wang

Vibhor Jain

John Joseph Pekarik

Khee Yong Lim

Fan Zhang

Qizhi Liu

Judson Robert Holt

Juan Boon Tan

Yung Fu Chong

Kien Seen Daniel Chong

Kenneth J Stein

Ming Zhu

Darin A Chan

Pinghui Li

Robert J Gauthier, Jr

Elgin Kiok Boone Quek

Soh Yun Siah

Shaoqiang Zhang

Tze Ho Simon Chan

Kian Ming Tan

Laiqiang Luo

Zhiqiang Teo

Fangxin Deng

Danny PakChum Shum

Kian Hui Goh

Cancan Wu

Thanh Hoa Phung

The present disclosure relates to a structure which includes a semiconductor substrate, a recessed shallow trench isolation structure within the semiconductor substrate, and a gate structure provided at least partially over the recessed shallow isolation structure.

Wrap-around memory circuit

Structures for a junction field-effect transistor and methods of forming a structure for a junction field-effect transistor. The structure comprises a first gate on a top surface of a semiconductor substrate, a second gate beneath the top surface of the semiconductor substrate, and a channel region in the semiconductor substrate. The first gate is positioned between a source and a drain, and the channel region positioned between the first gate and the second gate.

Junction field-effect transistors

A structure including a semiconductor layer having a body region of a first conductivity type and a first electrode including a doped region of a second conductivity type in the semiconductor layer is provided. The doped region is adjacent to the body region. The doped region includes a first portion and a second portion extending laterally from the first portion. The first portion has a first width and the second portion has a second width. The first width is greater than the second width. A ferroelectric layer is arranged on the semiconductor layer over the body region. A second electrode is arranged on the ferroelectric layer. The first portion and the second portion of the doped region partially underlap the second electrode.

Memory structures and methods of forming the same

The present disclosure relates to semiconductor structures and, more particularly, to transistor with wrap-around extrinsic base and methods of manufacture. The structure includes: a substrate; a collector region within the substrate; an emitter region over the substrate and which comprises silicon based material; an intrinsic base; and an extrinsic base overlapping the emitter region and the intrinsic base; an extrinsic base overlapping the emitter region and the intrinsic base; and an inverted 'T' shaped spacer which separates the emitter region from the extrinsic base and the collector region from the emitter region.

Transistor with wrap-around extrinsic base

The present disclosure relates to semiconductor structures and, more particularly, to bipolar transistors and methods of manufacture. The structure includes: an intrinsic base region; an emitter region above the intrinsic base region; a collector region under the intrinsic base region; and an extrinsic base region comprising metal material, and which surrounds the intrinsic base region and the emitter region.

Bipolar transistors

A structure includes a photodetector including alternating p-type semiconductor layers and n-type semiconductor layers in contact with each other in a stack. Each semiconductor layer includes an extension extending beyond an end of an adjacent semiconductor layer of the alternating p-type semiconductor layers and n-type semiconductor layers. The extensions provide an area for operative coupling to a contact. The extensions can be arranged in a cascading, staircase arrangement, or may extend from n-type semiconductor layers on one side of the stack and from p-type semiconductor layers on another side of the stack. The photodetector can be on a substrate in a first region, and a complementary metal-oxide semiconductor (CMOS) device may be on the substrate on a second region separated from the first region by a trench isolation. The photodetector is capable of detecting and converting near-infrared (NIR) light, e.g., having wavelengths of greater than 0.75 micrometers.

Multi-semiconductor layer photodetector and related method

A non-volatile memory device is provided. The non-volatile memory device includes a substrate having an active region, a source region, a drain region, and a floating gate. The source region and the drain region may be arranged in the active region, the drain region may be arranged adjacent to the source region. The source region and the drain region may define a channel region therebetween. The floating gate may be arranged over the active region, and may include a first section over the channel region, a plurality of second sections over the drain region, and a connecting section arranged between the first section and the plurality of second sections.

Non-volatile memory devices with asymmetrical floating gates

The present disclosure relates to semiconductor structures and, more particularly, to transistor with wrap-around extrinsic base and methods of manufacture. The structure includes: a substrate; a collector region within the substrate; an emitter region over the substrate and which comprises mono-crystal silicon based material; an intrinsic base under the emitter region and comprising semiconductor material; and an extrinsic base surrounding the emitter and over the intrinsic base.

A resistive random access memory (RRAM) device may be provided, including: a base layer, a vertical electrode stack arranged over the base layer, where the vertical electrode stack may include alternating mask elements and first electrodes, and each first electrode may include an extended portion extending beyond at least one side surface of at least one mask element adjoining the first electrode, a switching layer arranged along the extended portion of each first electrode and along the at least one side surface of the at least one mask element adjoining the first electrode, and a second electrode including a surface in contact with the switching layer. The RRAM device may have a 3D structure.

RRAM devices and methods of forming RRAM devices

A nonvolatile memory device is provided. The nonvolatile memory device comprises an n-doped source, an n-doped drain, and a doped region in a first p-well in a substrate. A floating gate may be arranged over the first p-well, whereby the doped region may be arranged at least partially under the floating gate.

Nonvolatile memory device with a doped region between a source and a drain and integration schemes

A nonvolatile memory device is provided. The nonvolatile memory device comprises an active region surrounded by an isolation structure. A floating gate may be arranged over the active region, the floating gate having a first end and a second end over the isolation structure. A first doped region may be provided in the active region adjacent to a first side of the floating gate and a second doped region may be provided in the active region adjacent to a second side of the floating gate. A first capacitor may be provided over the floating gate, whereby a first electrode of the first capacitor is electrically coupled to the floating gate. A second capacitor may be provided, whereby a first electrode of the second capacitor is over the isolation structure and adjacent to the floating gate.

Single well one transistor and one capacitor nonvolatile memory device and integration schemes

A memory device is provided. The memory device includes an active region in a substrate, an electrically-isolated electrode, and a dielectric layer. The electrically-isolated electrode is disposed over the active region. The dielectric layer is disposed between the electrically-isolated electrode and the active region and has a first dielectric portion having a first thickness and a second dielectric portion having a second thickness.

Semiconductor non-volatile memory devices

A nonvolatile memory device is provided. The device comprises a memory transistor. A first capacitor is coupled to the memory transistor. A second capacitor is coupled to the memory transistor. The second capacitor comprises a first electrode and a second electrode. The first capacitor and the second capacitor are connected to separate input terminals.

One transistor two capacitors nonvolatile memory cell

The embodiments herein relate to semiconductor memory devices and methods of forming the same. A semiconductor memory device is provided. The semiconductor memory device includes a dual-gate transistor and a memory cell. The memory cell is adjacent to the dual-gate transistor, wherein the memory cell and the dual-gate transistor share a common electrode.

Growing community of inventors

Singapore, Singapore

Xinshu Cai