Changxin Memory Technologies, Inc.

Xinran Liu

Chunyang Wang

Gongyi Wu

Yachao Xu

Changli Zhu

Bo Shao

Yong Lu

Longyang Chen

ZhiCheng Shi

Zhenxing Li

Yule Sun

Ruiqi Zhang

Juncai Li

A semiconductor structure and a manufacturing method therefor are provided. The semiconductor structure includes: a substrate; a plurality of connection pads disposed on a surface of the substrate; and a plurality of electrode pillars, disposed on the substrate and connected to the plurality of connection pads in a one-to-one correspondence. Each electrode pillar includes a first conductor layer and a second conductor layer that are alternately distributed in a direction perpendicular to the substrate. A material of the first conductor layer is different from a material of the second conductor layer. A side surface of the first conductor layer is recessed inward relative to a side surface of the second conductor layer.

Semiconductor structure and manufacturing method therefor

Embodiments provide a semiconductor structure and a fabricating method. The semiconductor structure includes: a substrate, where a trench is formed in the substrate; a conductive layer positioned in the trench, where the conductive layer includes a first conductive layer and a second conductive layer, the second conductive layer is positioned on the first conductive layer, and a projection area of a bottom of the second conductive layer within the trench is greater than a projection area of a top of the first conductive layer within the trench; a dielectric layer positioned between the conductive layer and an inner wall of the trench, where a top of the dielectric layer is lower than the top of the first conductive layer; an isolation layer positioned on the conductive layer; and a void defined by the isolation layer, the conductive layer, the dielectric layer, and a side wall of the trench.

Semiconductor structure and method for fabricating same

Embodiments of the present disclosure relate to the field of semiconductor structures, and provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base; a plurality of first conductive structures, located on a surface of the base and distributed at intervals along a first direction; a plurality of second conductive structures, located on the surface of the base, and the plurality of second conductive structures and the plurality of first conductive structures being arranged alternately; and a plurality of support structures, located on the surface of the base and a given one of the plurality of support structures being located between a given one of the plurality of first conductive structures and a given one of the plurality of second conductive structures.

Semiconductor structure and manufacturing method thereof

Embodiments of the present disclosure provide a method for obtaining parameters of a semiconductor structure, a method for obtaining a detection standard and a detection method. The method for obtaining parameters of a semiconductor structure includes: obtaining a semiconductor structure, the semiconductor structure including a substrate and a capacitor support structure on the substrate, the capacitor support structure having a plurality of capacitor holes therein, the capacitor holes penetrating the capacitor support structure in a thickness direction of the capacitor support structure; removing some height of the capacitor support structure; obtaining a test pattern, the test pattern being a pattern exposed at a top of the remaining capacitor support structure; and in the test pattern, obtaining a spacing between the capacitor holes at predetermined positions on the basis of a predetermined direction.

Method for obtaining parameters of semiconductor structure, method for obtaining detection standard and detection method

The present disclosure provides a semiconductor device and a method for manufacturing the same, and relates to the field of semiconductor technologies. The manufacturing method includes: providing a substrate and forming a film layer stack structure thereon; etching the film layer stack structure to form a first region containing a through hole through which the substrate is exposed and a second region containing a hole section through which the substrate is not exposed; and patterning and etching the second region to remove the film layer stack structure within the second region.

Semiconductor device and method for manufacturing the same

A method for forming a capacitor via includes: providing a to-be-processed wafer, the to-be-processed wafer including a substrate and a first dielectric layer and a first mask layer that are sequentially formed on a surface of the substrate; etching the first mask layer according to a compensated first etching parameter, to form a first patterned layer extending in a first etching direction; sequentially forming a second dielectric layer and a second mask layer on a surface of the first patterned layer; etching the second mask layer and the second dielectric layer according to a compensated second etching parameter, to form a second patterned layer extending in a second etching direction; and etching the first dielectric layer with the first patterned layer and the second patterned layer together as a capacitor pattern, to form a capacitor via.

Method for forming capacitor via

A method for predicting an inclination angle of an etched hole can include operations as follows. A preset change range of an etching rate of an etching device for an object to be etched on a surface of a monitored sample in different operation stages is determined. An etching rate change curve of the etching device for the object to be etched on the surface of a monitored sample in a current operation stage is acquired. When the etching rate change curve exceeds the preset change range, it is determined that an inclination angle of an etched hole of an etched product currently etched by the etching device exceeds a preset angle.

Method and device for predicting inclination angle, and method and device for monitoring etching device

Embodiments of the present application provide a process monitoring method and a process monitoring system. The process monitoring method includes: acquiring a semiconductor structure on which an etch process is performed in an etch chamber, and forming a corresponding test structure based on the semiconductor structure; acquiring first theoretical mass of the test structure after the etch process is theoretically performed; placing the test structure in the etch chamber to actually perform the etch process, and acquiring first residual mass of the test structure after the etch process is actually performed; and determining, based on the first theoretical mass and the first residual mass, whether an etch state of the etch process performed in the etch chamber is normal.

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Hefei, China

Xinran Liu