Integrated Device Technology, Inc.

Xinqing Chen

Yuan Yuan Zhang

HaiQi Liu

Yanbo Wang

ChangXi Xu

An apparatus includes a first circuit and a second circuit. The first circuit may be configured to generate a waveform in response to a frequency of an input clock signal and a threshold frequency. The second circuit may be configured to generate a control signal in response to a type of the waveform. The type of the waveform may comprise at least one of pulses and a steady state. The control signal may have a first state when the type of the waveform is the pulses and a second state when the type of the waveform is the steady state. A width of the pulses may be based on the threshold frequency.

Fast-response references-less frequency detector

An apparatus comprising an analog circuit and a digital circuit. The analog circuit may be configured to (i) receive pulses generated in response to a comparison of a feedback signal and a reference signal, (ii) filter the pulses when a frequency of the feedback signal is close to a frequency of the reference signal and (iii) generate an enable signal in response to the filtered pulses. The digital circuit may be configured to generate an output signal representing a lock status between (i) the feedback signal and (ii) the reference signal. The lock status may be determined (a) during a decision window based on a number of pulses of the reference signal and (b) when the enable signal is active (B) the decision window may be repeated periodically until the enable signal is not active.

Fast-response hybrid lock detector

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an intermediate signal in response to an input clock signal operating at a frequency. The first circuit may modify the input clock signal according to a threshold frequency to generate a waveform for the intermediate signal. The waveform of the intermediate signal may have at least one of (i) pulses and (ii) a steady state. The second circuit may be configured to generate a control signal in response to the intermediate signal. The second circuit may modify the intermediate signal to generate the control signal. The control signal may have a first state when the intermediate signal has pulses. The control signal may have a second state when the intermediate signal has the steady state.

Fast-response reference-less frequency detector

The invention concerns an apparatus comprising an analog circuit and a digital circuit. The analog circuit may be configured to generate an enable signal in response to (i) a comparison of a width of an up pulse and a pre-determined width and (ii) a comparison of a width of a down pulse and the pre-determined width. The up pulse and the down pulse may be generated in response to a comparison of a feedback signal and a reference signal. The enable signal may be active when both the comparisons are within a pre-determined threshold. The digital circuit may be configured to generate an output signal representing a lock status between (i) the feedback signal and (ii) the reference signal. The lock status may be determined (a) during a decision window based on a number of pulses of the reference signal and (b) when the enable signal is active.

Methods and systems for peak detection as part of automatic gain control in high-speed communications are provided. A peak detection system uses a portion of an input signal to generate a reference signal for comparison with the input signal. The comparison produces a differential error signal that is in turn used to produce one or more full swing pulses based on the comparison. A pulse counter counts the pulses, and if the count in a single clock cycle is above a determined threshold, a binary error signal is set to indicate a need for correction.

Growing community of inventors

Shanghai, China

Xinqing Chen