Omnivision Technologies, Inc.

Xinping James He

Datong Chen

Tiemin Zhao

Hongli Yang

Chih-huei Wu

Qingwei Shan

Tai-Ching Shyu

Xiaodong Luo

Jizhang Shan

Hongjun Li

Kimble Dong

Henry Yang

Quingwei Shan

A CMOS image sensor having blooming reduction mechanisms is disclosed. The image sensor can include a plurality of pixels arranged in rows and a timing and control circuit in electrical communication with the plurality of pixels. The timing and control circuit includes a readout module configured for outputting a first row of pixels exposed for a first exposure period, outputting a second row of pixels exposed for the first exposure period after outputting the first row of pixels, and thereafter outputting a third row of pixels exposed for a second exposure period different than the first exposure period, the third row of pixels being between the first and second rows of pixels.

Image sensors with blooming reduction mechanisms

Embodiments of the present invention are directed to a plurality of light sensor cells disposed in a substrate in a shared pixel arrangement. Common readout circuitry is used to simultaneously read out image information from a group of light sensor cells. The image information from the group of light sensor cells is added together simultaneously and coupled to auto-focus circuitry and/or preview circuitry to provide for better lens adjustments and preview display.

Image sensor with simultaneous auto-focus and image preview

An improved active pixel sensor soft reset circuit for reducing image lag while maintaining low reset kTC noise. The circuit pulls down the sensor potential to a sufficiently low level before the soft reset function is completed. The level to which the sensor potential is pulled is set between 0 and the critical potential at which the reset transistor will be on when the soft reset function begins. The timing of the pull down function is such that the sensor is stabilized at the low potential before the soft reset function completes. In one embodiment, the sensor potential is pulled down using a pull-down circuit, which may consist of a CMOS type inverter. In another embodiment, the sensor potential is pulled down by the bit line. Two ways in which the bit line may be pulled down are natural discharge, or by increasing the bias on the loading transistor. Two ways in which the bias on the loading transistor may be increased are a biasing circuit, or by using a pull-down transistor. The active pixel sensor may be implemented with any suitable sensor technology, such as photodiode, photogate, or pinned diode.

APS soft reset circuit for reducing image lag

The active pixel includes a photodiode, a transfer gate, and a reset transistor. The photodiode is substantially covered with an overlying structure, thus protecting the entire surface of the photodiode from damage. This substantially eliminates potential leakage current sources, which result in dark current. In one embodiment, the photodiode is covered by a FOX region in combination with the transfer gate.

Active pixel having reduced dark current in a CMOS image sensor

The active pixel includes a photodiode, a reset transistor, and a pixel output transistor. The photodiode is substantially covered with a protective structure, thus protecting the entire surface of the photodiode from damage. This substantially eliminates potential leakage current sources, which result in dark current. The protective structure has a photodiode contact formed therein to electrically connect the photodiode to the pixel output transistor.

A method for protecting an image sensor die is disclosed. The method comprises forming a plurality of image sensor die having micro-lenses onto a semiconductor wafer. Then, a protective layer is formed over the image sensor die. After the protective layer has been formed, and without any removal step of the protective layer, the wafer is diced to separate the plurality of image sensor die. Finally, the image sensor die are mounted onto an integrated circuit package and the protective layer is removed.

Sacrificial protective layer for image sensors and method of using

A CMOS image sensor that has reduced transistor count is disclosed. The individual pixels are formed by a pinned photodiode and a transfer transistor. An output node receives the signal from the photodiode via the transfer transistor. The output node is shared between multiple pixels. Further, a reset transistor is coupled between a selectable low voltage rail Vor a high voltage reference Vand the output node. The gate of an output transistor is then coupled to the output node. Both the reset transistor and output transistors are shared between multiple pixels.

CMOS image sensor using shared transistors between pixels with dual pinned photodiode

In a CMOS image sensor, it is important to control the exposure time or gain. For varying changes in ambient light, the exposure time of the array must be changed. The present invention describes a method for controlling the exposure time or gain to ensure a smooth and fast change in the brightness of the obtained image. If the exposure time is the be decremented or incremented, then the gain control is increased or decreased, respectively to smooth out the changes in image brightness. This substantially reduces image flicker.

Method of fast automatic exposure or gain control in a MOS image sensor

A method of reading out a pixel signal from a pixel is disclosed. The method comprises first capturing a first black reference signal from the pixel prior to the pixel starting an integration period. Next, after completion of the integration period, a pixel signal is captured. Next, a second black reference signal is captured following completion of the integration period. Finally, the first black reference signal, second black reference signal, and pixel signal is output.

Method and apparatus kTC noise cancelling in a linear CMOS image sensor

The image sensor includes a first group and a second group of column readout circuits for reading out pixel signals from said pixels. The total number of column readout circuits in each group is substantially less than the number of columns in the image sensor pixel array. Further included is a multiplexer bus system having selection switches for selectively switching pixel signals from a block of pixels in a column as input into the first group of column readout circuits. The multiplexer bus system also selectively switches pixel signals from another block of pixels in a column as input into a second group of column readout circuits. However, when the first group of column readout circuits is reading and storing said pixel signals, the second group of column readout circuits is transferring out the processed signals. Thus, the first and second groups work alternately.

CMOS image sensor having reduced numbers of column readout circuits

A CMOS camera image sensor that may be combined with additional CMOS camera image sensors to form a multiple-camera security monitoring system. Each CMOS image sensor includes phase-locked loop circuitry. The phase-locked loop circuitry receives a reference input signal and in response thereto synchronizes the video output of the CMOS image sensor to the reference input signal. In one configuration, one of the CMOS image sensors provides the reference signal, while in another configuration, the reference input signal may come from an external circuit. Each CMOS image sensor also includes state selection circuitry. The state selection circuitry allows the video output from the CMOS image sensor to be displayed on,, or all of a display. Thus, the video signals from multiple CMOS image sensors may be displayed on a video monitor simultaneously.

Analog video monitoring system using a plurality of phase locked CMOS image sensors

A method for reducing dark current in a photodiode is disclosed. The photodiode comprises a N-well formed in a P-substrate. The method comprises doping the surface of said N-well with a nitrogen dopant. Alternatively, an oxygen or silicon dopant may be used. Still alternatively, a silicon oxynitride layer may be formed over the N-well.

Surface passivation to reduce dark current in a CMOS image sensor

In a CMOS image sensor, it is important to control the exposure time or gain. For varying changes in ambient light, the exposure time of the array must be changed. The present invention describes a method for controlling the exposure time or gain. Each of the intensities of the pixels in a frame is analyzed to provide an indication of the number of pixels having an intensity above or below multiple predetermined thresholds. This information is then used to change the exposure time. The magnitude of change in the exposure time is also determined by the number of pixels having an intensity above or below multiple predetermined thresholds, as the case may be.

The present invention is directed to an analog delay line for a color CMOS image sensor which is compatible with MOS fabrication technology. The invention allows for the simultaneous reading of pixel signals from two rows of pixels so that combinations of signals from pixels in different rows may be obtained. The delay line includes a set of storage capacitors on which the pixel signals are stored, and a means for writing the signals from the pixels onto the capacitors in sequence. The stored analog pixel signals may then be read out from the delay line at the appropriate time so that they may be combined with pixel signals from adjacent pixels in different rows. In one embodiment, two delay lines are used, so that pixel signals from a current row can be written into one delay line, while the pixel signals from a previous row are being read out from the other delay line. In another embodiment, a single delay line is used in combination with a single pixel delay circuit. When the single pixel delay circuit is used, the pixel signals from a previous row are read out from the delay line and temporarily stored in the single pixel delay circuit, one at a time, shortly after which the pixel signals from the next row are written into the delay line. The pixel signals from the single pixel delay circuit are then read out at the same time that the pixel signals from the next row are being read in, so that signals from adjacent pixels in adjacent rows are available to the processing circuitry at the same time.

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San Jose, CA, United States of America

Xinping James He