Intel Corporation

Xinning Wang

Barbara A Chappell

Marni Nabors

Sukru Yemenicioglu

Quan Shi

Prashant S Sawkar

Nikolay Ryzhenko

Sivakumar Venkataraman

Integrated circuit structures having front side signal lines and backside power delivery are described. In an example, an integrated circuit structure includes a plurality of gate lines extending over a plurality of semiconductor nanowire stack or fin channel structures within a cell boundary. A plurality of trench contacts is extending over a plurality of source or drain structures within the cell boundary, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A first signal line, a second signal line, a third signal line, and a fourth signal line are over the plurality of gate lines and the plurality of trench contacts within the cell boundary. A backside power delivery line is coupled to one of the plurality of trench contacts within the cell boundary.

Integrated circuit structure with front side signal lines and backside power delivery

A method and apparatus provide a digital circuit including dynamic logic that minimizes circuit-path delay, residue logic, and circuit area. The method and apparatus use a library of circuit cells to produce a digital circuit design using a mapping algorithm. The mapping algorithm firstly determines an arrangement of circuit cells to minimize the delay in the circuit design, secondly determines an arrangement of circuit cells to minimize the residue logic for the circuit design, thirdly determines an arrangement of circuit cells to minimize the circuit area for the circuit design, and then repeats the process for each node in the circuit until the best circuit design is produced in accordance with pre-determined criteria.

Method and apparatus for improving digital circuit design

Growing community of inventors

Portland, OR, United States of America

Xinning Wang