Southeast University

Other

Wuxi Hongrui Bio-pharma-tech Co., Ltd.

Xinning Liu

Jun Yang

Chao Chen

Longxing Shi

Yuan Chen

Na Bai

Hong Chang

Yingcheng Xia

Yifeng Deng

Jiafeng Zhu

Yue Feng

Cai Gong

Fei Pan

Weiwei Shan

Yang Zhang

Yang Sun

Chao Wu

Yuan Zhuang

Longning Qi

Luhong Tang

Xin Fang

Shuang Qiu

Haolin Gu

Ajuan Dai

Jinfeng Ma

Ze Wang

Lingyan Xu

Yaqing Cao

Xiaomin Xu

Ruixia Jiang

A high energy efficiency switched-capacitor power converter includes the transmission gates T-T, the capacitors C-C, the load capacitor CL, and resistors, PMOS tubes and NMOS tubes. The power converter converts a stable input voltage of 3V into an output voltage of 1V by means of charge transfer. In the state of timing sequence, the on-chip capacitor C, the capacitor Cand the load capacitor CL are charged in series. In the state of timing sequence, the capacitor Cand the capacitor Care connected in parallel to the capacitor CL to supplement the charge loss due to load for the capacitor CL. When the establishment is completed, the voltages across the capacitor C, the capacitor C, and the capacitor CL are basically the same. At this time, the voltage drop across the switch tube approximates 0 V during the charge transfer process.

High energy efficiency switched-capacitor power converter

An ultra-low-power mode control circuit for a power converter includes four modules: a level shift circuit, a start circuit, a static clamp circuit, and a control circuit. When a chip is powered on and a core voltage has not been established, the control circuit firstly starts a power source built-in clock to support operation of the power converter. When the core voltage is established, the control circuit determines whether to switch to an external clock according to a level of a mode selection signal. After the core voltage is powered down, the control circuit automatically wakes up the built-in clock to work.

Ultra-low-power mode control circuit for power converter

A wide voltage trans-impedance amplifier includes a first P-channel metal oxide semiconductor (PMOS) transistor PM, a second PMOS transistor PM, a third PMOS transistor PM, a fourth PMOS transistor PM, a fifth PMOS transistor PM, a first bias voltage VB, a second bias voltage VB, a third bias voltage VB, a first N-channel metal oxide semiconductor (NMOS) transistor NM, and a second NMOS transistor NM. A common-gate amplifier detects a change of an input voltage, and a negative feedback is constructed by injecting a current into a current mirror to achieve a low input impedance. The trans-impedance amplifier uses a common-gate amplifier to monitor an input voltage and uses a current mirror to perform the transconductance enhancement on an input transistor, while ensuring a relatively high loop gain.

Wide voltage trans-impedance amplifier

A low-temperature drift ultra-low-power linear regulator includes eight PMOS transistors, two resistors, two capacitors and three NMOS transistors. The eight PMOS transistors include PMOS transistor PMto PMOS transistor PM. The two resistors include resistor Rand resistor R. The two capacitors include capacitor Cand capacitor C. The three NMOS transistors include NMOS transistor NM, NMOS transistor NMand NMOS transistor NM. From right to left, the linear regulator includes a PTAT voltage core starting circuit, a PTAT voltage core circuit, a negative temperature characteristic generating circuit and a driver stage closed-loop control circuit. PM-PMform a feedback circuit. The feedback circuit clamps the current flowing through PMto be proportional to PMto obtain a temperature-stable output voltage, and can dynamically adjust the gate voltage of PMaccording to the change of load current to output different currents according to the load demand.

Low-temperature drift ultra-low-power linear regulator

A positioning method using height-constraint-based extended Kalman filter, suitable for a GNSS navigation and positioning system, comprises: obtaining an estimated state value of a current epoch by using an extended Kalman filter algorithm and according to an estimated state value of a previous epoch; constraining a positioning height of the current epoch by establishing a height constraint condition, so as to obtain an optimum estimated value of the current epoch and a corresponding mean square error, wherein the optimum estimated value satisfies the height constraint condition; further correcting the estimated state value by using a pseudorange obtained from the mean square error and a measured Doppler shift residual to obtain a final estimated state value of the current epoch, thus more accurately obtaining positioning information of a target to be positioned in the current epoch and enhancing the accuracy of GNSS navigation and positioning.

Positioning method using height-constraint-based extended Kalman filter

A circuit for improving process robustness of sub-threshold SRAM memory cells serves as an auxiliary circuit for a sub-threshold SRAM memory cell. The output of the circuit is connected to PMOS transistors of the sub-threshold SRAM memory cell and substrate of PMOS transistors in the circuit. The circuit includes a detection circuit for threshold voltages of the PMOS transistors and a differential input and single-ended output amplifier. The circuit changes the substrate voltage of the PMOS transistors in the sub-threshold SRAM memory cell and the PMOS transistors in the circuit in a self-adapting manner by detecting threshold voltage fluctuations of PMOS and NMOS transistor resulted from process fluctuations and thereby regulates the threshold voltages of the PMOS transistors, so that the threshold voltages of the PMOS and NMOS transistors match. The circuit improves the noise margin of sub-threshold SRAM memory cells and the process robustness of sub-threshold SRAM memory cells.

Circuit for enhancing robustness of sub-threshold SRAM memory cell

Disclosed is a noise current compensation circuit. The circuit is provided with two input and output terminals A and B, and two control terminals CON and CONF. The control terminals control a work mode (work state and pre-charge state) of the compensation circuit. The compensation circuit consists of 7 PMOS transistors and 8 NMOS transistors. In the normal work state, by detecting changes of potential change rate of two signal lines in an original circuit, the noise current compensation circuit automatically enables one end of the original circuit that discharges slowly to discharge a signal more slowly, and enables one end of the original circuit that discharges rapidly to discharge a signal more rapidly, thus eliminating the influence of the noise current on the circuit and providing assistance for correct identification of subsequent circuit signals. The current compensation circuit can be used for an SRAM bit line leakage current compensation circuit, because the existence of a large leakage current on the SRAM bit line leads to the decreasing of a voltage difference between two ends of the bit line, resulting in that a subsequent circuit cannot correctly identify a signal.

Noise current compensation circuit

A dynamic voltage scaling system based on on-chip monitoring and voltage prediction is disclosed, comprising a main circuit that has integrated on-chip monitoring circuits, a supply voltage scaling module, and voltage converters, wherein, the supply voltage scaling module comprises a sampling and statistics module designed to calculate the error rate of the main circuit in the current time slice, a state recording module designed to record the error rate and the corresponding supply voltage, an error prediction module, and a state transition probability generation module; the error prediction module predicts the error trend of the main circuit in a future time slice according to the state recording module and the state transition probability generation module, and generates regulation signals and sends to the corresponding voltage converters, so as to generate the voltage required for operation of the entire main circuit.

Dynamic voltage scaling system based on on-chip monitoring and voltage prediction

The present invention designs and synthesizes the ascorbyl ester derivatives of the aryl (ethanoic) propanoic acid non-steroidal anti-inflammatory medicaments, such as ibuprofen, ketoprofen and naproxen, and addition salt of the derivatives with pharmaceutical acid or pharmaceutical alkaline. The non-steroidal anti-inflammatory medicament which takes the ibuprofen as the representative is a common antipyretic analgesic medicament. The invention has remarkable antipyretic and analgesic effects and good safety except for anti-inflammatory effect, thus being not only suitable for adults, but also suitable for the elderly people, infants and children. The aryl (ethanoic) propanoic acid ascorbyl ester can be converted into ascorbyl ester derivatives and the addition salts of the derivatives with pharmaceutical acid or pharmaceutical alkaline, which can improve the water solubility thereof, facilitate intravenously administration, reduce the onset time, improve the bioavailability, reduce the stimulation effect to gastrointestinal tract, and enhance the penetrating capacity to hemato encephalic barrier, and can be used as a novel medicament to be applied for antiphlogistic, antipyresis, analgesia, treatment of arthritis, dysmenorrheal, multiple sclerosis, pneumonia cystic fibrosis and patent ductus arteriosus of premature infants, and prevention and treatment of cerebral apoplexy, hypoxic-ischemic brain damage, senile dementia and certain cancers.

Aryl (ethanoic) propanoic acid ascorbyl ester, preparation method thereof and medicament containing the same

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Nanjing, China

Xinning Liu