Applied Materials, Inc.

Xinhai Han

Bok Hoen Kim

Masaki Ogata

Juan Carlos Rocha-Alvarez

Nagarajan Rajagopalan

Deenesh Padhi

Amit Kumar Bansal

Zhijun Jiang

Ganesh Balasubramanian

Michael Wenyoung Tsiang

Heung Lak Park

Thomas E Nowak

Todd J Egan

Jianhua Zhou

Jian J Chen

Ramprakash Sankarakrishnan

Mohamad A Ayoub

Edward W Budiarto

Terrance Y Lee

Jeongmin Lee

Patrick Reilly

Shahid Shaikh

Sergey Starik

Dmitriy Panasyuk

Daemian Raj Benjamin Raj

Wenjiao Wang

Praket Prakash Jha

Thomas Jongwan Kwon

Shailendra Srivastava

Kristopher R Enslow

Nikhil Sudhindrarao Jorapur

Chuan Ying Wang

Tza-Jing Gung

Sai Susmita Addepalli

Gregory Eugene Chichkanoff

Ryeun Kwan Kim

Sang Hyuk Kim

Mukund Srinivasan

Ji Ae Park

Joshua Maher

Allen Ko

Kesong Hu

Er-Xuan Ping

Sanjeev Baluja

Chentsau Chris Ying

Zheng John Ye

Lin Zhang

Hang Yu

Mayur G Kulkarni

Sanjay G Kamath

Hyung Jin Park

Srinivas Guggilla

Chuanxi Yang

Jason K Foster

Sung Hyun Hong

Majid K Shahreza

Liyan Miao

Tsutomu Kiyohara

Long Lin

Myung Hun Ju

Jin Chul Son

Saiprasanna Gnanavelu

Jennifer Y Sun

Philip Allan Kraus

Mehul B Naik

Anantha K Subramani

Jian Li

Yue Chen

Kang Sub Yim

Dmitry A Dzilno

Bencherki Mebarki

Edward P Hammond

Jonghoon Baek

Shuran Sheng

Juan Carlos Rocha

Nitin Khurana

Sohyun Park

Kaushik Comandoor Alayavalli

Xuesong Lu

Yongjing Lin

Steven D Marcus

Hidehiro Kojiri

Andrew V Le

Joseph C Werner

Shaunak Mukherjee

Allison Yau

Yang Guo

Ndanka O Mukuti

Jang Seok Oh

Vu Ngoc Tran Nguyen

Arkajit Roy Barman

Yusheng Zhou

Alok Jain

Mitesh Sanghvi

Thuy Britcher

Abhigyan Keshri

Ryan Yamase

Shamik Patel

Ran Ding

Ramcharan Sundar

Methods of forming 3D NAND devices are discussed. Some embodiments form 3D NAND devices with increased cell density. Some embodiments form 3D NAND devices with decreased vertical and/or later pitch between cells. Some embodiments form 3D NAND devices with smaller CD memory holes. Some embodiments form 3D NAND devices with silicon layer between alternating oxide and nitride materials.

Methods of forming 3D NAND structures with decreased pitch

An electronic device manufacturing system capable of obtaining metrology data associated with a deposition process performed on a substrate according to a process recipe, wherein the deposition process generates a plurality of layers on a surface of the substrate. The manufacturing system can further obtain an expected profile associate with the process recipe, wherein the expected profile comprises a plurality of values indicative of a desired thickness for a plurality of layers of the process recipe. The manufacturing system can further generate a correction profile based on the metrology data and the expected profile, wherein the correction profile comprises a deposition time offset value for at least one layer of the plurality of layers. The manufacturing system can further generate an updated process recipe by applying the correction profile to the process recipe and cause a deposition step to be performed on the substrate according to the updated process recipe.

Methods and mechanisms for adjusting film deposition parameters during substrate manufacturing

Exemplary methods of forming semiconductor structures may include forming a silicon oxide layer from a silicon-containing precursor and an oxygen-containing precursor. The methods may include forming a silicon nitride layer from a silicon-containing precursor, a nitrogen-containing precursor, and an oxygen-containing precursor. The silicon nitride layer may be characterized by an oxygen concentration greater than or about 5 at. %. The methods may also include repeating the forming a silicon oxide layer and the forming a silicon nitride layer to produce a stack of alternating layers of silicon oxide and silicon nitride.

Modified stacks for 3D NAND

A faceplate for a substrate process chamber comprises a first and second surface. The second surface is shaped such that the second surface includes a peak and a distance between the first and second surface varies across the width of the faceplate. The second surface of the faceplate is exposed to a processing volume of the process chamber. Further, the faceplate may be part of a lid assembly for the process chamber. The lid assembly may include a blocker plate facing the first surface of the faceplate. A distance between the blocker plate and the first surface is constant.

Faceplate having a curved surface

Methods and systems are described for generating assessment maps. A method includes receiving a first vector map comprising a first set of vectors each indicating a distortion of a particular location on a substrate and generating a second vector map indicating a change in direction of a magnitude of the distortion of the particular location on the substrate. The method further includes generating a third vector map comprising vectors reflecting reduced noise in distortions across the plurality of locations on the substrate and generating a fourth vector map projecting a direction component of each vector component in the third set of vectors to a radial direction. The method further includes generating a fifth vector map by grouping the vectors of the fourth set of vectors and determining a magnitude associated with each group of vectors.

Analyzing in-plane distortion

Exemplary substrate processing systems may include a chamber body defining a transfer region. The systems may include a first lid plate seated on the chamber body. The first lid plate may define a plurality of apertures through the first lid plate. The systems may include a plurality of lid stacks equal to a number of the plurality of apertures. The systems may define a plurality of isolators. An isolator may be positioned between each lid stack and a corresponding aperture of the plurality of apertures. The systems may include a plurality of annular spacers. An annular spacer of the plurality of annular spacers may be positioned between each isolator and a corresponding lid stack of the plurality of lids stacks. The systems may include a plurality of manifolds. A manifold may be seated within an interior of each annular spacer of the plurality of annular spacers.

Hot showerhead

A method of processing a substrate according to a PECVD process is described. Temperature profile of the substrate is adjusted to change deposition rate profile across the substrate. Plasma density profile is adjusted to change deposition rate profile across the substrate. Chamber surfaces exposed to the plasma are heated to improve plasma density uniformity and reduce formation of low quality deposits on chamber surfaces. In situ metrology may be used to monitor progress of a deposition process and trigger control actions involving substrate temperature profile, plasma density profile, pressure, temperature, and flow of reactants.

PECVD process

Examples disclosed herein relate to a method and apparatus for cleaning and repairing a substrate support having a heater disposed therein. A method includes (a) cleaning a surface of a substrate support having a bulk layer, the substrate support is disposed in a processing environment configured to process substrates. The cleaning process includes forming a plasma at a high temperature from a cleaning gas mixture having a fluorine containing gas and oxygen. The method includes (b) removing oxygen radicals from the processing environment with a treatment plasma formed from a treatment gas mixture. The treatment gas mixture includes the fluorine containing gas. The method further includes (c) repairing an interface of the substrate support and the bulk layer with a post-treatment plasma. The post-treatment plasma is formed from a post-treatment gas mixture including a nitrogen containing gas. The high temperature is greater than or equal to about 500 degrees Celsius.

High-temperature chamber and chamber component cleaning and maintenance method and apparatus

Exemplary semiconductor processing systems may include a processing chamber and an electrostatic chuck disposed at least partially within the processing chamber. The electrostatic chuck may include at least one electrode and a heater. A semiconductor processing system may include a power supply to provide a signal to the electrode to provide electrostatic force to secure a substrate to the electrostatic chuck. The system may also include a filter communicatively coupled between the power supply and the electrode. The filter is configured to remove or reduce noise introduced into the chucking signal by operating the heater while the electrostatic force on the substrate is maintained. The filter may include active circuitry, passive circuitry, or both, and may include an adjustment circuit to set the gain of the filter so that an output signal level from the filter corresponds to an input signal level for the filter.

Power supply signal conditioning for an electrostatic chuck

Methods, systems, and non-transitory computer readable medium are described for generating assessment maps for corrective action. A method includes receiving a first vector map including a first set of vectors each indicating a distortion of a particular location of a plurality of locations on a substrate. The method further includes generating a second vector map including a second set of vectors by rotating a position of each vector in the first set of vectors. The method further includes generating a third vector map including a third set of vectors based on vectors in the second set of vectors and corresponding vectors in the first set of vectors. The method further includes generating a fourth vector map by subtracting each vector of the third set of vectors from a corresponding vector in the first set of vectors. The fourth vector map indicates a planar component of the first vector map.

Methods of forming 3D NAND devices are discussed. Some embodiments form 3D NAND devices with a control gate and a floating gate disposed between a first insulating layer and a second insulating layer. A conformal blocking liner surrounds the floating gate and electrically isolates the control gate from the floating gate. Some embodiments form 3D NAND devices with decreased vertical and/or later pitch between cells.

3-D NAND control gate enhancement

Embodiments described herein relate to methods and materials for fabricating semiconductor devices, such as memory devices and the like. In one embodiment, a memory layer stack includes materials having differing etch rates in which one material is selectively removed to form an airgap in the device structure. In another embodiment, silicon containing materials of a memory layer stack are doped or fabricated as a silicide material. In another embodiment, a silicon nitride material is utilized as an interfacial layer between oxide containing and silicon containing layers of a memory layer stack.

Multi-layer stacks for 3D NAND extendability

Exemplary methods of semiconductor processing may include flowing a silicon-containing precursor, a nitrogen-containing precursor, and diatomic hydrogen into a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region of the semiconductor processing chamber. The methods may also include forming a plasma of the silicon-containing precursor, the nitrogen-containing precursor, and the diatomic hydrogen. The plasma may be formed at a frequency above 15 MHz. The methods may also include depositing a silicon nitride material on the substrate.

Systems and methods for depositing high density and high tensile stress films

Growing community of inventors

Santa Clara, CA, United States of America

Xinhai Han