Yangtze Memory Technologies Co., Ltd.

Xingwei Tang

Lu Guo

Guangchang Ye

Chaofan Xie

An example of the present application discloses a memory device and operating method thereof, a memory system and operating method thereof, wherein the memory device includes: an array of memory cells; a peripheral circuit coupled to the array of memory cells and configured to: obtain a first result corresponding to a target location in the array of memory cells at an initial target read voltage; perform multiple adjustments to the initial target read voltage, and obtain the first result corresponding to the target location at the target read voltage after each of the adjustments respectively; determine a valley voltage in accordance with a plurality of the obtained first results.

Memory device and its operating method, memory system and operating method thereof

The present application provides a memory system, an operation method of a memory system, and a memory controller, and relates to the technical field of storage. In the solution provided by the present application, a memory comprises a plurality of blocks and at least one reserved block. Upon detecting a fail page among pages included in the plurality of blocks, a memory controller can acquire data in the fail page, and back up the data in the fail page to one backup page in the at least one reserved block.

Memory system, operation method of memory system, and memory controller

Examples of the present application disclose a memory device and operating method thereof, a memory system and operating method thereof, wherein the memory device includes: an array of memory cells; peripheral circuit coupled to the array of memory cells and configured to: obtain the first state corresponding to at least one code word formed by a preset number of memory cells at the target read voltage; perform multiple adjustments to the target read voltage, and obtain a first state corresponding to the at least one of the code words at the read voltage after each of the adjustments respectively; determine a valley voltage in accordance with a variation trend of the relationship of size between the number of flipped bits and the first preset value indicated by a plurality of the obtained first states.

Memory device and operating method thereof, memory system and operating method thereof

According to one aspect of the present disclosure, a memory device is provided. The memory device may include an array of memory cells, including a plurality of memory cells. A preset number of memory cells form a code word. The memory device may include peripheral circuit coupled to the array of memory cells. The peripheral circuit may be configured to obtain the first result corresponding to the code word at the target read voltage. The peripheral circuit may be configured to adjust the target read voltage in accordance with the first result corresponding to the code words at the target read voltage. The peripheral circuit may be configured to obtain the first result corresponding to the code words at the adjusted read voltage. The peripheral circuit may be configured to determine a valley voltage in accordance with a plurality of the first results.

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Wuhan, China

Xingwei Tang