Changxin Memory Technologies, Inc.

Beijing Superstring Academy of Memory Technology

Xingsong Su

Deyuan Xiao

Weiping Bai

Guangsu Shao

Mengkang Yu

Yunsong Qiu

Yi Jiang

Youming Liu

Lianhong Wang

Zhan Ying

Zhen Zhou

Qiang Zhang

Yuhan Zhu

Pan Yuan

A semiconductor structure includes a substrate and a conductive structure located above the substrate. The conductive structure includes a plurality of first conductive structures and second conductive structures that are spaced apart from each other and extend in a first direction. Lengths of the first conductive structures and lengths of the second conductive structures vary in steps. The lengths of the plurality of first conductive structures and the lengths of the plurality of second conductive structures vary in steps. The first conductive structures and the second conductive structures form Word Lines (WLs).

Semiconductor structure and manufacturing method therefor, and memory

A preparation method for the capacitor structure includes: forming a dielectric layer on a first electrode, wherein, the dielectric layer includes a first amorphous layer and a high dielectric constant layer which are stacked, the first amorphous layer maintaining an amorphous structure after annealing, and the high dielectric constant layer being formed by crystallizing an initial dielectric constant layer after annealing; and forming a second electrode on the dielectric layer. Since the first amorphous layer remains an amorphous structure after annealing, electron transport can be suppressed, thereby reducing the leakage current of the capacitor structure.

Preparation method for capacitor structure, capacitor structure, and memory

A method for manufacturing a semiconductor structure includes providing a substrate; forming mutually parallel first trenches extending along a first direction in the substrate and first isolation structures filling the first trenches; forming mutually parallel second trenches extending along a second direction in the substrate and in the first isolation structures, the first and second trenches dividing the substrate to form active pillars, and a depth of the second trenches being less than that of the first trenches; forming second isolation structures alternately arranged with the first isolation structures along the second direction at bottoms of the second trenches, top surfaces of the second isolation structures being lower than bottom surfaces of the second trenches located in the first isolation structures; forming bit line structures on the second isolation structures; and forming word line structures above the bit line structures.

Semiconductor structure, method for manufacturing same and memory

Embodiments relate to a three-dimensional semiconductor structure and a formation method thereof. The three-dimensional semiconductor structure includes: a substrate; and a device structure positioned on a top surface of the substrate. The device structure includes memory rows arranged at intervals along a first direction, each of the memory rows includes memory cells arranged at intervals along a second direction and a gap between adjacent two of the memory cells, and each of the memory cells includes a first stacked layer and a word line structure. The word line structure includes a first part positioned in the first stacked layer and a second part extending out of the first stacked layer along the first direction. At least adjacent two of the memory rows exist, and the second part of the memory cell in one of the memory rows extends into the gap in another one of the memory rows.

Three-dimensional semiconductor structure and formation method thereof

Disclosed in the embodiments of the present disclosure are a semiconductor structure and method for manufacturing same, and a memory. The semiconductor structure includes: a plurality of first active columns arranged in an array along a first direction and a second direction, a plurality of first electrodes located in first grooves arranged at intervals, a plurality of first dielectric layers, and a second electrode covering surfaces of the first dielectric layers. The first direction and the second direction are perpendicular to the extension direction of the first active column, and the first direction is intersected with the second direction. Each first electrode covers a side wall of one of the first active columns. Each first groove surrounds a surface of each first active column. Each first dielectric layer covers the side wall of one of the first electrodes and a bottom of a gap between two adjacent first electrodes.

Semiconductor structure and method for manufacturing same, and memory

The present disclosure provides a capacitor and a manufacturing method thereof, and a semiconductor device. The capacitor includes a plurality of bottom electrodes, a top electrode structure, a dielectric layer, and a gap filling layer, where the top electrode structure is formed on one side of each of the plurality of bottom electrodes, one side of the dielectric layer is in contact with the plurality of bottom electrodes and the other side is in contact with the top electrode structure, and the gap filling layer fills remaining gaps between the plurality of bottom electrodes.

Capacitor and manufacturing method thereof, and semiconductor device

Embodiments provide a semiconductor structure. The semiconductor structure includes a substrate, a dielectric layer arranged on the substrate, and a plurality of memory cell layers. The plurality of memory cell layers are spaced in the dielectric layer along a first direction, and projections of any adjacent two of the plurality of memory cell layers on the substrate are overlapped. Each of the plurality of memory cell layers includes a plurality of memory cells spaced along a second direction. According to the embodiments, the plurality of memory cell layers are spaced in the dielectric layer along a direction perpendicular to the substrate, and each of the plurality of memory cell layers has a plurality of memory cells therein; and a source, a channel and a drain in each of the plurality of memory cells are arranged along a direction parallel to the substrate.

2T0C semiconductor structure

A memory device and a manufacturing method therefor. A film-stack structure is formed on a substrate, the film-stack structure includes sacrificial layers and active layers alternately stacked in a first direction. Part of the film-stack structure located in a first area is removed. A plurality of first grooves spaced apart from each other and extend in a second direction are formed, where the substrate is exposed from the first grooves to divide the active layers located in the first area into a plurality of active pillars spaced apart from each other. The sacrificial layers located in the first and second areas are removed. Part of the active layers located in the second area is removed, to form a plurality of step-shaped connection layers on an end of the second area away from the first area. Gate material layers are formed to cover the connection layers and the active pillars.

Memory device and manufacturing method therefor

Embodiment relates to the field of semiconductor technology, and more particularly, to a memory, a semiconductor structure and a formation method thereof. The formation method of the present disclosure includes: providing a substrate; forming a plurality of groups of support pillars spaced apart along a first direction in the substrate, each of the plurality of groups of support pillars being spaced apart along a second direction, the first direction intersecting with the second direction; forming a support layer filling up top gaps between adjacent two of the support pillars; forming an epitaxial pillar on a top of each of the support pillars respectively by means of an epitaxial growth process; and forming a capacitor structure on a surface of a structure jointly constituted by each of the epitaxial pillars and each of the support pillars.

Memory, semiconductor structure and formation method thereof

A semiconductor structure and a method for manufacturing a semiconductor structure are provided. The method for manufacturing the semiconductor structure includes: a substrate is provided: a plurality of semiconductor channels arrayed in a first direction and a second direction are formed on the substrate: a plurality of bit lines extending in the first direction are formed, in which the bit lines is located in the substrate: and a plurality of word lines extending in the second direction are formed, in which two word lines adjacent to each other in the first direction are spaced apart from each other in a direction perpendicular to a surface of the substrate: and a sidewall conductive layer is formed, in which the sidewall conductive layer is located above one of the two word lines adjacent to each other, and is arranged in the same layer as the other of the two word lines.

Semiconductor structure and method for manufacturing semiconductor structure

Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: providing a base; forming a bottom electrode layer on the base, wherein a crystal structure of the bottom electrode layer includes a tetragonal crystal system; forming a first dielectric layer on a surface of the bottom electrode layer by using the bottom electrode layer as a seed layer, wherein a crystal structure of the first dielectric layer includes a tetragonal crystal system; and forming a first current blocking layer on a surface of the first dielectric layer.

Semiconductor structure and manufacturing method thereof

A method for manufacturing a semiconductor structure includes: providing a substrate; patterning the substrate to form a substrate layer and a plurality of silicon pillars; forming an oxide layer on a surface of the substrate layer between the plurality of silicon pillars; forming an isolation structure on the oxide layer, gaps being provided between upper part of the isolation structure and the silicon pillars; forming a first conductive layer in the gaps; partially removing the isolation structure and retaining the isolation structure below the first conductive layer to form an isolation layer; and forming a dielectric layer and a second conductive layer on surfaces of the isolation layer, the oxide layer, the first conductive layer and the silicon pillars.

Method for manufacturing semiconductor structure, semiconductor structure and semiconductor memory

A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes: a substrate; a laminate structure arranged on the substrate and including first semiconductor layers spaced apart from each other in a direction perpendicular to a top surface of the substrate, each first semiconductor layer including channel areas spaced apart from each other in a first direction, and first doped areas and second doped areas, each first doped area being arranged on one side of a respective one of the channel areas in a second direction, each second doped area being arranged on another side of the respective one of the channel areas in the second direction; and a word line structure including word lines extending in the first direction, an edge of each word line being flush with an edge of a respective one of the channel areas in the second direction.

Semiconductor structure and method for forming semiconductor structure

The application relates to an electrode layer, a capacitor and methods for electrode layer and capacitor manufacture. The method for electrode layer manufacture comprises the following steps: forming a first electrode layer, the first electrode layer comprising a doped Titanium Nitride (TiN) layer; and forming a second electrode layer on the surface of the first electrode layer, the second electrode layer comprising a TiN layer or a work function layer.

Electrode layer, capacitor and methods for electrode layer and capacitor manufacture

A capacitor structure includes two electrodes arranged oppositely and a dielectric layer located between the two electrodes, wherein the dielectric layer includes at least two perovskite layers stacked; an amorphous layer is provided between every two adjacent perovskite layers; two outermost perovskite layers of the at least two perovskite layers are in contact with the two electrodes, respectively.

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Hefei, China

Xingsong Su