Intel Corporation

Xingping Ruan

Xiang Sean Zhou

Xiao Liang Hu

Zhiming Li

Jie Gandalf Yan

Terrence Trausch

Robert Pebly

A system includes a host processor () and a peripheral device (). The host processor () is coupled to the peripheral device () by a Peripheral Component Interconnect Express (PCIe) compliant link. The peripheral device () can include logic circuitry to identify, based on an application using the device and the host processor (), a read to write ratio utilized by the application; and provide the read to write ratio to the host processor (). The host processor () comprising logic circuitry to send a command signal to a device in communication with the hardware processor across a peripheral component interconnect express (PCIe) compliant link, the command signal indicating a transmission (TX) lane to receive (RX) lane ratio, the TX lane to RX lane ratio corresponding to the read to write ratio identified by the peripheral device (); and receive an indication that the device is capable of supporting asymmetric TX and RX ratios.

Asymmetric transmission (TX) and receive (RX) lanes in a point-to-point interconnect using a peripheral component interconnect express (PCIE) resources in a computer system

Growing community of inventors

Shanghai, China

Xingping Ruan