Freescale Semiconductor,inc.

Nxp Usa, Inc.

Xinghai Tang

Hector Adrian Sanchez

Gayathri Bhagavatheeswaran

Carlos A Greaves

Jim P Nissen

Gayathri A Bhagavatheeswaran

A phase locked loop having a normal mode and a burn-in mode. The logic portion is coupled to a logic power supply terminal and includes a clock receiver coupled to a phase frequency detector. The analog portion has a charge pump coupled to the phase frequency detector and to an analog power supply terminal. The analog portion also has a voltage controlled oscillator coupled to the charge pump at an analog node and to the analog power supply terminal. The phase locked loop has a node control circuit that is coupled to the analog node during the burn-in mode that controls a voltage at the analog node sufficiently below a voltage at the analog power supply terminal to avoid over-stressing the charge pump and the voltage controlled oscillator during the burn-in mode.

Phase locked loop with burn-in mode

An IC includes: a substrate having a thick oxide portion and a thin oxide portion; a load circuit disposed on the thin oxide portion and coupled between a supply node and a virtual supply node; and a current source circuit and protection circuit disposed on the substrate. The current source circuit has an output coupled to the virtual supply node and is operable to provide a voltage at the virtual supply node. The protection circuit includes a sensing portion and a protection portion. The sensing portion is coupled to the virtual supply node and is operable to detect the voltage at the virtual supply node. The protection portion is coupled to the sensing portion and is operable, in response to the sensed voltage, to prevent a difference in voltage between the voltage at the virtual supply node and a second voltage at the supply node from exceeding a maximum voltage.

Over voltage protection for a thin oxide load circuit

A voltage translation circuit () provides an output analog voltage signal that has a translated voltage of the voltage of an input analog voltage signal over a range of values of the input analog voltage signal. The voltage translation circuit includes an input stage () having a circuit node and an input transistor () coupled between the circuit node and a power supply terminal, wherein a gate of the input transistor is coupled to receive the input analog voltage signal; a current path circuit () in parallel with the input transistor, wherein the current path includes a first transistor coupled between the circuit node and the power supply terminal; and a circuit coupled to provide a variable body bias voltage to a body of the first transistor.

Voltage translation circuit

A level shifter includes first, second and third capacitively configured transistors, first and second switching transistors, and an inverting circuit. The first capacitively configured transistor has a first terminal that receives an input signal. Second and third capacitively configured transistor each have first terminal coupled to a second terminal of the first capacitively configured transistor. The second capacitively configured transistor is coupled in series with a first switching transistor that is also coupled to a first power supply terminal. The third capacitively configured transistor is coupled in series with a second switching transistor that is also coupled to a second power supply terminal.

AC coupled level shifter

A phase locked loop (PLL) includes a phase frequency detector powered by a first analog supply voltage; a charge pump powered by a second analog supply voltage, different from the first analog supply voltage; a voltage controlled oscillator (VCO) powered by a third analog supply voltage, different from the first and second analog supply voltages, wherein a frequency of the VCO is controlled by a control voltage; and a supply voltage provider having a first circuit node coupled to a fourth analog supply voltage, a second circuit node which provides the first analog supply voltage, a third circuit node which provides the second analog supply voltage, and a fourth circuit node which provides the third analog supply voltage, and a current compensator coupled to one of the second, third, or fourth circuit nodes, wherein the current compensator provides a variable current draw based on the control voltage.

Phase locked loop with power supply control

A clock receiver () on an integrated circuit () includes a programmable AC voltage divider () for receiving, through an input capacitor (), a clock signal () from a clock generator () off the integrated circuit and for outputting a modified signal that has a reduced voltage swing, an inverter () coupled to the programmable voltage divider, and a common mode setting circuit (), coupled to an input and an output of the inverter. The common mode setting circuit sets and maintains a common mode at the input of the inverter in response to a voltage at the input of the inverter and a voltage at the output of the inverter. The strength of transistors in the common mode tracking circuit tracks the strength of transistors in the inverter such that the common mode at the input to the inverter tracks a trip point of the inverter.

Common mode tracking receiver

A method for a phase-locked loop (PLL) in an integrated circuit, wherein the PLL comprises a voltage-controlled oscillator (VCO). The method includes, in a training mode: (1) setting a control voltage of the VCO at a first voltage level; (2) increasing the control voltage of the VCO from the first voltage level to a second voltage level, until a loss of the feedback signal is detected; and (3) storing an indicator value corresponding to the second voltage level of the control voltage of the VCO. The method further includes, in a normal mode: (1) monitoring a voltage level of the control voltage of the VCO by generating a monitored indicator value corresponding to the voltage level of the control voltage of the VCO; and (2) asserting the loss of feedback signal based on a comparison of the monitored indicator value and the indicator value.

Phase-locked loop having a feedback clock detector circuit and method therefor

An anti-gate leakage programmable capacitor including at least one capacitor having a first terminal coupled to a first node and a second terminal, a second node, and a control circuit which selectively couples the second terminal of the capacitor to the second node or which drives the second terminal to the same voltage as the first node. In one embodiment, the programmable capacitor includes multiple capacitors, an amplifier having an input coupled to the first node and an output, and a switch circuit coupled to the second node, to each second terminal of each capacitor and to the amplifier output. The switch circuit selectively switches each second terminal of each capacitor between the amplifier output and the second node. The switch circuit may include pairs of switches each controlled by a corresponding select signal to selectively switch a corresponding capacitor between the reference node and the output of the amplifier.

Anti-gate leakage programmable capacitor

A level shifter circuit including first and second circuits and a protection layer. The first circuit receives an input signal and switches first and second nodes to opposite states within a first voltage range between first and second supply voltages. The second circuit switches the third and fourth nodes to opposite states within a second voltage range between third and fourth supply voltages in response to switching of the first and second nodes. The protection layer couples the first and second nodes to third and fourth nodes via respective first and second isolation paths. The isolation paths operate to keep the first and second nodes within the first voltage range and to keep the third and fourth nodes within the second voltage range. Isolation enables the use of thin gate-oxide devices for speed while extending the voltage range beyond the maximum voltage allowable for a single thin gate-oxide device.

Cascadable level shifter cell

A high speed output buffer including an input circuit providing first and second signals within a first voltage range having a first common mode voltage, an AC interface receiving the first and second signals and providing first and second preliminary drive signals, a detection and correction circuit that corrects a state of the first preliminary drive signal AC coupled to the first signal, first and second drive circuits receiving the preliminary drive signals and providing first and second drive signals, where the first drive circuit operates within a second voltage range having a greater common mode voltage and where the second drive circuit operates within a third voltage range, and an output that switches an output node within a voltage range that is greater than a maximum voltage range. The first, second and third voltage ranges are each within the maximum voltage range suitable for thin-gate devices.

High speed output buffer with AC-coupled level shift and DC level detection and correction

A programmable PLL including a receiver, a phase frequency detector, a charge pump, and a VCO. The receiver includes a programmable capacitor voltage divider that shifts voltage of an input clock to provide a level-shifted clock. The AC interface includes a state detection and correction circuit that ensures proper state of the level-shifted clock. The PLL includes a pulse delay modulator for generating delayed clock control signals. The VCO includes a programmable phase control circuit that dynamically adjusts phase using the delayed clock control signals. The VCO circuit includes a ring oscillator circuit with one or more phase control nodes. The programmable phase control circuit selectively couples devices to the phase control node using the clock control signals to adjust phase. The devices may be capacitors or transistors, each switched using switches controlled by the delayed clock control signals. The capacitors may be metal capacitors or semiconductor transistor capacitors.

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Cedar Park, TX, United States of America

Xinghai Tang