Mips Technologies, Inc.

Arm Finance Overseas Limited

Xing Yu Jiang

Kjeld Svendsen

Karagada Ramarao Kishore

Ying-wai Ho

Vidya Rajagopalan

Maria Ukanwa

A processor and system for latest producer tracking In one embodiment, the processor includes an operand renamer circuit that includes a register rename map, a producer tracking circuit that includes a producer tracking map, and a results buffer allocater circuit that includes a results buffer free list. Control logic modifies in-register status values stored in the register rename map based on producer tracking status values stored in the producer tracking map. The producer tracking status values stored in the producer tracking map are modified based on buffer identification values output by the results buffer allocater circuit.

Latest producer tracking in an out-of-order processor, and applications thereof

A conditional move instruction implemented in a processor by forming and processing two decoded instructions, and applications thereof. In an embodiment, the conditional move instruction specifies a first source operand, a second source operand, and a third operand that is both a source and a destination. If the value of the second operand is not equal to a specified value, the first decoded instruction moves the third operand to a completion buffer register. If the value of the second operand is equal to the specified value, the second decoded instruction moves the value of the first operand to the completion buffer. When the decoded instruction that performed the move graduates, the contents of the completion buffer register is transferred to a register file register specified by the third operand.

Conditional move instruction formed into one decoded instruction to be graduated and another decoded instruction to be invalidated

Methods for latest producer tracking in a processor. In one embodiment, the method includes the steps of (1) writing a physical register identification value in a first register rename map location specified by a first instruction, (2) writing a first in-register status value in a second register rename map location specified by the first instruction, (3) writing a producer tracking status value at a producer tracking map location specified by the physical register identification value, and (4) modifying, upon graduation of the first instruction, the first in-register status value only if the producer tracking map location stores the producer tracking status value written in step (3). Other methods are also presented.

Method for latest producer tracking in an out-of-order processor, and applications thereof

A processor core and a method for distributive scoreboard scheduling in an out-of-order processor pipeline are described herein. In an embodiment, control logic appends operand availability bits to each instruction. The appended operand availability bits form a distributive scoreboard for each instruction. The appended operand availability bits are propagated together with the instruction through multiple stages of the processor pipeline. An instruction dispatch buffer stores the instruction and the operand availability bits. A dispatch controller determines when an instruction is to be issued. The determination is based, at least in part, on the operand availability bits stored in the instruction dispatch buffer.

System and method for propagating operand availability prediction bits with instructions through a pipeline in an out-of-order processor

Floating-point units (FPUs) and processors having a 'flush-to-nearest' operating mode that provides improved accuracy over a conventional 'flush-to-zero' mode. The FPU or processor includes an operand processing section and an operand flush section. For each floating-point operation, the operand processing section receives and processes one or more input operands to provide a preliminary result. The operand flush section determines whether the preliminary result falls within one of a number of ranges of values and sets the preliminary result to one of a number of set values if the preliminary result falls within one of the ranges. In a specific implementation, a first range of values is defined to include values greater than zero and less than half of a minimum normalized number (i.e., 0&#x3c;|y|&#x3c;+a/2), a second range of values is defined to include values equal to or greater than +a/2 and less than +an, (i.e., a/2&#x2266;|y|&#x3c;a), and the preliminary result is set to zero if it falls within the first range and to +aor &#x2212;a(depending on the sign bit) if it falls within the second range.

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Palo Alto, CA, United States of America

Xing Yu Jiang