Chartered Semiconductor Manufacturing Ltd (corporation)

Xing Yu

Ting Cheong Ang

Shyue Fong Quek

Ying Keung Leung

Jun Song

Hong Yang

Shao Kai

Shyue Pong Quek

A process for fabricating a MOSFET device, featuring source/drain extension regions, formed after the utilization of high temperature processes, such as heavily doped source/drain regions, has been developed. Disposable insulator spacers are formed on the sides of doped, SEG silicon regions, followed formation of a gate insulator layer, and an overlying gate structure, on a region of the semiconductor substrate located between the doped SEG silicon regions. The temperature experienced during these process steps result in the formation of the heavily doped source/drain, underlying the SEG silicon regions. Selective removal of the disposable spacers, allows the source/drain extension regions to be placed in the space vacated by the disposable spacers, adjacent to the heavily doped source/drain region. Insulator spacers are then used to fill the spaces vacated by removal of the disposable spacers, directly overlying the source/drain extension regions. Additional iterations include the use of an L shaped spacer, overlying the source/drain extension region, as well as the formation of metal silicide, on the doped SEG silicon regions, and on the gate structures.

Method for forming MOSFET device having source/drain extension regions located underlying L shaped spacers

Process to fabricate a source-drain extension

Process to fabricate a novel source-drain extension

A method for integrating the dual gate and double poly capacitor processes to fabricate an analog capacitor integrated circuit device is described. An isolation region is provided separating a first active area from a second active area in a semiconductor substrate. A first gate oxide layer is formed overlying the semiconductor substrate in both active areas. A first polysilicon layer is deposited overlying the first gate oxide layer and the isolation region. An capacitor dielectric layer comprising an oxide layer and a nitride layer is deposited overlying the first polysilicon layer. The capacitor dielectric layer and first polysilicon layer are etched away where they are not covered by a mask to form a first polysilicon gate electrode in the first area and a polysilicon capacitor bottom plate and overlying capacitor dielectric overlying the isolation region. The first gate oxide layer is removed in the second area and a thinner second gate oxide layer is formed in the second area. A second polysilicon layer is deposited overlying the second gate oxide layer, bottom capacitor plate and capacitor dielectric, and the first polysilicon gate electrode. The second polysilicon layer is etched away where it is not covered by a mask to form a second polysilicon gate electrode in the second area and to form a top capacitor plate overlying the bottom capacitor plate having the capacitor dielectric layer therebetween.

Dual gate and double poly capacitor analog process integration

A method of fabricating a transistor, comprising the following steps. A silicon semiconductor substrate having a pad oxide portion within an active area is provided. A polysilicon layer is deposited over the silicon semiconductor substrate and over the pad oxide portion. A pad oxide layer is deposited over the polysilicon layer. Shallow isolation trench regions are formed on either side of the active area. The pad oxide layer is removed. The polysilicon layer is etched and removed over the pad oxide portion leaving polysilicon portions between the pad oxide portion and the shallow isolation trench regions. The pad oxide portion is replaced with a gate oxide portion. A gate conductor, having exposed side walls, is formed over the gate oxide portion and between the polysilicon portions. Sidewall spacers are formed on the exposed side walls of the gate conductor with the sidewall spacers contacting the polysilicon portions. Source/drain regions are formed in the active area under the sidewall spacers and under the polysilicon portions. A salicide portion is formed over the gate conductor and salicide portions are formed over the polysilicon portions, whereby the formation of the salicide layers over the polysilicon portions consumes a portion of the polysilicon portions leaving the remainder of the polysilicon layers to form shallow source/drain junctions underneath the polysilicon portion salicide portions.

Method of fabrication of a raised source/drain transistor

A new method for forming a cobalt disilicide film on shallow junctions with reduced silicon consumption in the fabrication of an integrated circuit is described. A semiconductor substrate is provided having silicon regions to be silicided. A cobalt layer is deposited overlying the semiconductor substrate and subjected to a first rapid thermal process whereby the cobalt is transformed to cobalt monosilicide where it overlies the silicon regions and wherein the cobalt not overlying the silicon regions is unreacted. The unreacted cobalt layer is removed. A dielectric layer is deposited overlying the substrate and the cobalt monosilicide layer. Silicon ions are implanted through the dielectric layer into the cobalt monosilicide layer. The substrate is subjected to a second rapid thermal process whereby the cobalt monosilicide is transformed to cobalt disilicide wherein the silicon ions implanted into the cobalt monosilicide layer act as a main (not sole) silicon source for the transformation to complete formation of a cobalt disilicide film in the manufacture of an integrated circuit.

Method to form CoSi.sub.2 on shallow junction by Si implantation

A method for forming a raised source and drain structure without using selective epitaxial silicon growth. A semiconductor substrate is provided having one or more gate areas covered by dielectric structures. Doped polysilicon structures are adjacent to the dielectric structures on each side and are co-planar with the dielectric structures from a CMP process. The first dielectric structures are removed to form gate openings and a liner oxide layer is formed on the bottom and sidewalls of the gate openings. Dielectric spacers are formed on the liner oxide layer over the sidewalls of the gate openings, and the liner oxide layer is removed from the bottom of the gate openings and from over the doped polysilicon structures. Source and drain regions are formed in the semiconductor substrate by diffusing impurity ions from the doped polysilicon layer. A gate oxide layer and a gate polysilicon layer are formed over the semiconductor structure and the gate polysilicon layer is planarized to form a gate electrode. In a key step, the dielectric spacers are removed to form spacer openings, and impurity ions are implanted through the spacer openings and annealed to form source and drain extensions. The dielectric spacers are reformed and a self-aligned silicide layer is formed on the doped polysilicon structure and the gate electrode. Alternatively, the self-aligned silicide layer can be formed prior to removing the dielectric spacers and implanting ions to form source and drain extensions.

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Singapore, Singapore

Xing Yu