Micron Technology Incorporated

Illinois Tool Works Inc.

China University of Mining and Technology

Paypal, Inc.

Huawei Technologies Co., Limited

Shanghai Unihertz E-commerce Co., Ltd.

Agold Communication (shanghai) Co., Ltd.

Xing Wang

Xu Zhang

Hao Chen

Mengli Sun

Adam Cohen

Chunmao Ran

David Stein

Avishay Meron

Zhen Gu

Xiaolai Zhu

Huachen Li

Liping Xu

Tian Liang

Zhong Xian Li

Bin Zhao

Xinghui Duan

Liu Yang

Qing Wang

He Cheng

Qianlong Wang

Deping He

Bo Li

Chenghui Peng

Guan Zhong Wang

Rui Ni

Tao Qu

Itzik Levi

Junjun Wang

Zhou Yang

Doron Hai-Reuven

He Zhang

Yuxiang Chen

Shenghua Bao

Wenyu Li

Qishan Zhang

Laibang Xue

Xueguo Lian

Huan Yang

Shengquan Wang

Guoqiang Han

Methods, systems, and devices for dynamic memory management operation are described. A memory system may store data in a first block that includes a first type of memory cells configured to store a single bit of information (e.g., single level cells (SLCs)). The memory system may set a flag associated with the data indicating whether the data includes secure information and is to remain in a block that includes SLCs after a memory management operation (e.g., a garbage collection operation). The memory system may store, as part of the memory management operation for the first block and based on the flag, valid data of the first block in a second block that includes SLCs or a third block that includes a second type of memory cells configured to store two or more bits of information.

Dynamic memory management operation

Placing an event into a particular cluster can allow various inferences about the event. A new payment transaction that looks similar to a previously identified cluster of mostly fraudulent payment transactions, for example, may be higher risk. The present disclosure includes structural data improvements to the way that online clustering of events (which may include web events and not just payment transactions) occurs. A new event can be classified into a particular segment very quickly using feature table searching, which can allow for better decision making when a short timeframe is required (e.g. transaction processing, online advertising, etc.).

Rapid online clustering

Methods, systems, and devices for memory management procedures for write boost mode are described. A memory system may receive a command to write data. The memory system may write the data to a first location of the memory system using a first mode for storing one bit per memory cell based on receiving the command. The memory system may select a first portion of the data to rewrite to the memory system using a second mode for storing two or more bits per memory cell based on one or more parameters satisfying one or more thresholds. The memory system may write the first portion of the data to a second location of the memory system using the second mode based on selecting the first portion of the data. The memory system may maintain a second portion of the data at the first location of the memory system.

Memory management procedures for write boost mode

Techniques are described herein for performing a flush operation for a write booster buffer of a memory system. The flush operation may include swapping valid blocks in the write booster buffer for invalid blocks in a storage space of the memory system. After swapping the blocks, the memory system may transfer the information from a first type of blocks that were formerly assigned to the write booster buffer to a second type of blocks in the storage space. In such a flush operation, space is made available in the write booster buffer with less latency than it would take to transfer information between blocks, thereby improving the performance of the write booster mode.

Write booster buffer flush operation

A connector having a head that holds a first component and a body connected to the head. The body has a central channel extending along a central axis of the connector, and the central channel receives a fastener. The body has at least two resilient legs. The resilient legs extend obliquely toward the central axis in a direction from the body to the head. The resilient legs engage with the fastener, to attach the connector to the fastener.

Connector

Methods, systems, and devices for validity mapping techniques are described. A memory device may use a change log to update a mapping that indicates whether data stored at respective physical addresses is valid. For example, the memory device may receive a command associated with data having a corresponding set of addresses (whether logical block addresses or physical addresses). The memory device may set an entry of the change log based on whether the set of addresses are consecutive. For example, the memory device may identify whether the set of addresses are consecutive and may set a flag in the entry of the change log to indicate whether the addresses are consecutive. Then, the memory device may update one or more entries of the mapping corresponding to the entry of the change log to indicate whether the addresses corresponding to the one or more entries of the mapping store valid data.

Validity mapping techniques

Methods, systems, and devices for unmap backlog in a memory system are described. A memory system may be configured to support receiving an unmap command from a host system and signaling, to the host system, an indication that the unmap command has been processed (e.g., handled, acknowledged). In response to the unmap command, the memory system may proceed with various unmap operations, which may include unmapping at least some of the associated addresses after indicating that the unmap command has been processed. For example, a memory system may implement an unmap backlog table to identify sections of addresses that are to be unmapped (e.g., after indicating that the unmap command has been processed). In some examples, the memory system may support various aspects of prioritization between unmap operations (e.g., background unmap operations) and other access operations such as read operations, write operations, or other access operations.

Unmap backlog in a memory system

A system includes a memory device having an array of memory cells coupled with a plurality of page buffers. At least a portion of the array is configured as single-level cell memory. A processing device is coupled to the memory device and includes cache, the processing device to perform operations including: detecting demand for the cache during a memory operation requiring access to the single-level cell memory; and causing metadata associated with the memory operation to be stored in one or more page buffers of the plurality of page buffers, the one or more page buffers operating as an extension of the cache available to the processing device.

Memory sub-system cache extension to page buffers of a memory array

Methods, systems, and devices for logical-to-physical (L2P) mapping compression techniques are described. A memory system may use an L2P mapping to map logical addresses to physical addresses of the memory system. The L2P mapping may be a hierarchical L2P mapping divided into multiple levels or subsets that are used to identify a physical address corresponding to a logical address. The memory system may write data to a set of physical addresses that are consecutively indexed and may set a flag in an entry of a second-level of the L2P mapping (e.g., of a three-level L2P mapping) to indicate that the entry is associated with a starting physical address of the consecutively indexed physical addresses. The memory system may subsequently read the data starting at the starting physical address based on the flag (e.g., bypassing reading an entry of a lowest-level of the L2P mapping to determine the physical address).

Logical-to-physical mapping compression techniques

Devices and techniques for data removal marking in a memory device are described herein. A delete command can be received at the memory device. A count of data portions in the delete command can be compared to determine whether the count is below a threshold. In response to determining that the count of data portions is below the threshold, the data portions can be written to a buffer. When a buffer full event is detected, a segment of an L2P data structure can be loaded into working memory of the memory device. Then, each record in the segment of the L2P data structure that has a corresponding entry in the buffer can be updated to mark the data as removable (e.g., invalid).

Data removal marking in a memory device

The present disclosure relates to a pipe holding clip that defines a widthwise direction, a heightwise direction, and a lengthwise direction. The pipe holding clip can include a base portion, a pair of oppositely-arranged lateral portions extending upward from the base portion, a pair of holding arms extending inward from the pair of lateral portions and extending toward the base portion, and a support portion. Two sides of the support portion can be connected to the base portion or the pair of lateral portions. The support portion can include a working surface having an arc shape recessed toward the base portion. The pipe holding clip can provide a suitable holding force to limit the movement of a clamped pipe in an axial direction of the pipe.

Pipe holding clip

The present application provides a fastening clip, which comprises a fastening pin and a fastening sleeve. The fastening pin can be inserted into the fastening sleeve, the fastening sleeve comprises a base and two pairs of retaining wings, the two pairs of retaining wings respectively extend downward from a lower surface of the base, and outer sides of at least one of the two pairs of retaining wings have raised ribs extending in a circumferential direction. The fastening clip of the present application can firmly fasten at least two plates.

Fastening clip

A fastener includes a fastening pin and a sleeve component disposed around the fastening pin and movable up and down relative to the fastening pin. The sleeve component includes fixing claws that are able to stretch outward and retract inward. A pin of the fastening pin comprises a small-diameter rod section and an upper large-diameter rod section. When the fixing claws move relative to the pin to abut against an outer surface of the upper large-diameter rod section, the fixing claws stretch outward, and the fastener is in a locked state. When the fixing claws move to the outside of the small-diameter rod section relative to the pin, the fixing claws retract inward, and the fastener is in a release state.

Fastener

Growing community of inventors

Shanghai, China

Xing Wang