Intel Corporation

Xing Jian Cai

Chung-Hao Chen

Michael J Castillo

Wei Qian

Ke W Wang

Srinivas Thota

Chi-Te Chen

Long Wang

Yihong Yang

Neffody E Kraskoff

Jue Chen

Wei Z Gao

Su Mi Sam

Some embodiments include apparatuses and electrical models associated with the apparatus. One of the apparatuses includes an integrated circuit having a die; a package substrate; first conductive connections coupled between the die and a first side of the package substrate; second conductive connections located on a second side of the package substrate opposite from the first side. The second conductive connections are coupled to the first conductive connections through conductive paths in the package substrate. The first conductive connections and the conductive connections are associated with an S-parameter of an electrical model of the integrated circuit package. The electrical model further includes at least one of a current value associated with a power rail of the integrated circuit package, an impedance target associated with a location at the integrated circuit package, and a mapping associated with the first and second conductive connections.

Platform power integrity design including package standard power integrity model and compact voltage regulator module model

In some embodiments a differential communication channel compensates for electrostatic discharge capacitance of an electrostatic discharge component by increasing an impedance of the differential communication channel near the electrostatic discharge component. Other embodiments are described and claimed.

Compensating for an electrostatic discharge capacitance load

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Palo Alto, CA, United States of America

Xing Jian Cai