Meta Platforms, Inc.

Xing Cindy Chen

Harikrishna Madadi Reddy

Junqiang Lan

Visalakshi Vaduganathan

Sujith Srinivasan

Guogang Hua

Chung-Fu Lin

Handong Li

Deepa Palamadai Sundar

Tuo Wang

A scalable hardware accelerator configured to compute video quality metrics is disclosed. In some embodiments, an accelerator for video quality metrics comprises an application-specific integrated circuit that includes a buffer memory configured to store at least a portion of a reference frame of a video and at least a corresponding portion of a distorted frame of a transcoded version of the video and that includes a processing unit configured to receive data from the buffer memory and compute a perception-based video quality metric for the distorted frame with respect to the reference frame.

Scalable accelerator architecture for computing video quality metrics

A disclosed computer-implemented method may include (1) selecting, from a video stream, a reference frame and a current frame, (2) collecting a reference histogram of the reference frame and a current histogram of the current frame, and (3) generating a smoothed reference histogram by applying a smoothing function to at least a portion of the reference histogram. In some examples, the computer-implemented method may also include (1) determining a similarity metric between the smoothed reference histogram and the current histogram and, (2) when the similarity metric is greater than a threshold value, applying weighted prediction during a motion estimation portion of an encoding of the video stream. Various other methods, systems, and computer-readable media are also disclosed.

Systems and methods for histogram-based weighted prediction in video encoding

Various features of a high performance hardware scaler are disclosed herein. In some embodiments, a hardware scaler comprises a first processing unit configured to perform preparation and scaling operations and a second processing unit configured to perform preparation and scaling operations. The first processing unit and the second processing unit alternatively switch between performing preparation and scaling operations when processing a current input pixel block such that the first processing unit performs scaling operations while the second processing unit performs preparation operations and the second processing unit performs scaling operations while the first processing unit performs preparation operations.

High performance hardware scaler

Growing community of inventors

Los Altos, CA, United States of America

Xing Cindy Chen