Globalfoundries Singapore Pte. Ltd.

Xinfu Liu

Xueming Dexter Tan

Eng Huat Toh

Kiok Boone Elgin Quek

Khee Yong Lim

Siow Lee Chwa

Yoke Leng Lim

Xiaohua Zhan

Xiao Mei Elaine Low

Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure comprises a semiconductor layer, a first raised source/drain region on the semiconductor layer, a second raised source/drain region on the semiconductor layer, a gate electrode laterally between the first raised source/drain region and the second raised source/drain region, a first airgap laterally between the first raised source/drain region and the gate electrode, and a second airgap laterally between the second raised source/drain region and the gate electrode. The gate electrode includes a first section and a second section between the first section and the semiconductor layer, the first section of the gate electrode has a first width, the second section of the gate electrode has a second width, and the first width is greater than the second width.

Field-effect transistors with airgap spacers

A device and a method for forming a device are disclosed. The method includes providing a substrate prepared with a device region. A device well having second polarity type dopants is formed in the substrate. A threshold voltage (V) implant is performed with a desired level of second polarity type dopants into the substrate. The Vimplant forms a Vadjust region to obtain a desired Vof a transistor. A co-implantation with diffusion suppression material is performed to form a diffusion suppression (DS) region in the substrate. The DS region reduces or prevents segregation and out-diffusion of the Vimplanted second polarity type dopants. A transistor of a first polarity type having a gate is formed in the device region. First and second diffusion regions are formed adjacent to sidewalls of the gate.

Semiconductor device with improved narrow width effect and method of making thereof

A device and methods of forming the device are disclosed. A substrate with a circuits component and a dielectric layer with interconnects is provided. A pad level dielectric layer is formed over the dielectric layer. A primary passivation layer is formed over the pad level dielectric layer with pad interconnects. The substrate is subjected to an alloying process. During the alloying process, the primary passivation layer prevents or reduces formation of hillocks on surfaces of the pad interconnects to improve surface smoothness of the pad interconnects. Pad openings are formed in the pad level dielectric layer to expose top surfaces of the pad interconnects. A cap dielectric layer is formed on the substrate and lines the primary passivation layer as well as the exposed top surfaces of the pad interconnects. A final passivation layer is formed on the substrate and covers the cap dielectric layer. The final passivation layer is patterned to form final passivation openings corresponding to the pad openings.

Reliable pad interconnects

High voltage devices and methods for forming a high voltage device are disclosed. The high voltage device includes a substrate prepared with a device isolation region. The device isolation region defines a device region. The device region includes at least first and second source/drain regions and a gate region defined thereon. A device well is disposed in the device region. The device well encompasses the at least first and second source/drain regions. A primary gate and at least one secondary gate adjacent to the primary gate are disposed in the gate region. The at least first and second source/drain regions are displaced from first and second sides of the primary gate.

High voltage transistor

Integrated circuits with a Hall effect sensor and methods for fabricating such integrated circuits are provided. The method includes forming a buried plate layer within a substrate and overlying a substrate base, where the buried plate layer is doped with an 'N' type dopant. A cover insulating layer if formed overlying the buried plate layer, and a plurality of contact points are formed adjacent to the cover insulating layer.

Growing community of inventors

Singapore, Singapore

Xinfu Liu