Sandisk Technologies Inc.

Western Digital Technologies, Inc.

S-tec Corporation

Hgst Technologies Santa Ana, Inc.

Stmicroelectronics Gmbh

Hgst Netherlands, B.v.

Xinde Hu

Richard David Barndt

Manuel Antonio d'Abreu

Anthony Dwayne Weathers

Nian Niles Yang

Zhenlei Shen

Chao Sun

Majid Nemati Anaraki

Yiwei Song

Sivagnanam Parthasarathy

Sergey Anatolievich Gorobets

Christopher John Petti

Jianmin Huang

Steven Theodore Sprouse

Daniel Lee Helmick

Dejan Vucinic

Lei Chen

Uday Chandrasekhar

Peter Grayson

Shayan Srinivasa Garani

Neil David Hutchison

Rodney Brittner

Eran Sharon

Idan Alrod

Ariel Navon

Jiahui Yuan

Gautam Ashok Dusija

Niles Yang

Daniel Edward Tuers

Aaron Keith Olbrich

Grishma Shah

Nicholas Julian Richardson

Yongke Sun

Dillip Kumar Dash

Lanlan Gu

Bin Wu

Levente Peter Jakab

Swati Bakshi

Alexei Naberezhnov

Rohit Komatineni

Wen Pan

Bijesh Rajamohanan

A data storage device includes a memory device and a controller coupled to the memory device. The memory device is arranged in a plurality of logical planes and the controller is configured to write log data and user data to separate planes within the memory device, such that the log data and user data are isolated from each other on separate planes. The controller is configured to read log data from one plane and user data on another plane simultaneously, where the log data and the user data are isolated from each other on separate planes.

Storing log and user data in SSD with independent plane operations

A data storage device includes a memory device that includes a plurality of zones of a zoned namespace and a controller coupled to the memory device. During operation, the controller maintains a window-based read and write monitor data structure to determine the read density and write density of each of the zones. The read density and write density are utilized to determine a cost for allocating wear leveling data for each zone. Based on the cost and the available storage capacity of the storage class memory, data, in a data management operation, is moved to either the storage class memory or the zone with the low cost. The host device is informed of the storage class memory usage for future data management operations.

Wear leveling methods for zoned namespace solid state drive

The present disclosure generally presents a method and apparatus to provide a bounded latency, where a device would report 'non-service' of a command at the defined system level timeout or earlier if the device was unable to successfully return the data to the host.

Bounded latency and command non service methods and apparatus

A Data Storage Device (DSD) includes a flash memory for storing data. Portions of the flash memory are grouped into logical groups based on at least one of a number of Program/Erase (P/E) cycles and a physical level location of the portions of the flash memory. A command performance latency is monitored for each logical group, and at least one polling time for each respective logical is set based on the monitored command performance latency for the logical group. The at least one polling time indicates a time to wait before checking whether a portion of the flash memory in the logical group has completed a command.

Flash memory polling

A soft information module is coupled between one or more flash memory devices and a decoder. The soft information module receives a putative value of one or more memory cells of the one or more flash memory devices based on a read of the one or more memory cells at an initial read level, and one or more respective indicators of whether the putative value was read at one or more respective different read levels offset from the initial read level, and receives a page indicator for the read. The soft information module determines a cell program region for the read based on the putative value, the one or more respective indicators, and the page indicator, identifies a predetermined confidence value for the region, and provides the confidence value to the decoder for association with the putative value, the confidence value being representative of a likelihood that the one or more memory cells was programmed to the putative value.

Soft information module

A non-volatile memory is configured to allow programming and erase at the sub-block level. In a sub-block erase, some of the memory cells can be selected for erase while others are not selected for erase, such as by leaving their word lines to float while applying the erase voltage to the well structure of the physical block to which the sub-blocks belong. Although a sub-block erase applies a lower electric field across the non-selected memory cells than the erase selected memory cells, it still places the non-selected memory cells under some degree of stress and can lead to erase disturb. To help manage this erase disturb, each sub-block has an associated erase disturb count, which is incremented when another sub-block of the same physical block is erased, but reset when the sub-block itself is erase. Once a count reaches a threshold value, the sub-block can be marked for remedial action, such as refresh or garbage collection.

Non-volatile memory sub-block erasure disturb management scheme

Decoding logic is provided that is operational upon a data buffer to represent a plurality of variable nodes and a plurality of check nodes. For a respective one of the variable nodes, a vector component is selected from a confidence vector associated with the variable node. Using a respective one of the check nodes, a check node return value is calculated based on one or more other vector components from one or more other vectors and one or more vector indices corresponding to the one or more other vector components. The confidence vector is then updated based on the check node return value and an index for the check node return value, and a current state of a memory cell associated with the respective one of the variable nodes is determined based on a location of a primary one of multiple vector components within the updated confidence vector.

Reduced complexity non-binary LDPC decoding algorithm

A data storage device includes a non-volatile memory and a controller operationally coupled to the non-volatile memory. The controller is configured to access information stored at the non-volatile memory. The information includes a user data portion and an error correcting code (ECC) portion corresponding to the user data portion. The controller is further configured to modify the ECC portion in response to an error rate associated with the information exceeding a threshold. The one or more ECC parameters are modified without erasing or re-programming the user data portion.

Error correcting code adjustment for a data storage device

Systems and methods for controlling blocks in a memory device using a health indicator (such as the failed bit count) for the blocks are disclosed. However, the health indicator may exhibit noise, thereby resulting in an unreliable indicator of the health of the blocks in the memory device. In order to filter out the noise, a rolling average of the health indicator may be determined, and compared to the current health indicator. The comparison with the rolling average may indicate whether the current health indicator is an outlier, and thus should not be used. The health indicator may also be used to predict a future health indicator for different blocks in the memory device. Using the predicted future health indicator, the use of the blocks may be changed in order to more evenly wear the blocks.

System and method for utilizing history information in a memory device

A storage device with a memory may include memory block leveling that improves data retention by considering localized temperature. A block's distance from a heat source may result in variance of data retention. The localized temperature may be used to improve data retention through a relocation, refreshing, or leveling of blocks that considers their physical location on the die and/or in the package.

Data retention in a memory block based on local heating

A non-volatile memory system includes a plurality of non-volatile data memory cells arranged into groups of data memory cells, a plurality of select devices connected to the groups of data memory cells, a selection line connected to the select devices, a plurality of data word lines connected to the data memory cells, and one or more control circuits connected to the selection line and the data word lines. The one or more control circuits are configured to determine whether the select devices are corrupted. If the select devices are corrupted, then the one or more control circuits repurpose one of the word lines (e.g., the first data word line closet to the select devices) to be another selection line, thus operating the memory cells connected to the repurposed word line as select devices.

Non-volatile memory with dynamic repurpose of word line

Technology is described for selecting a group of reversible-resistance memory cells in which to store data based on information regarding switching the reversible-resistance memory cells from a first resistance state in which the reversible-resistance memory cells are in immediately after fabrication to a second resistance state for the first time after fabrication. Information regarding switching the reversible-resistance memory cells from the first resistance state to the second resistance state for the first time after fabrication may provide insight into factors including, but not limited to, endurance and data retention. In one aspect, a control circuit is configured to select a group of reversible-resistance memory cells in which to store data based on both the difficulty in switching from the first resistance state to the second resistance state for the first time after fabrication and a temperature of the data to be stored in the memory system.

Selecting reversible resistance memory cells based on initial resistance switching

A data storage device includes a memory. A method includes de-allocating a first region of a group of regions of the memory during a wear leveling process based on a determination that the first region is associated with a first tag of a set of tags. Each region of the group of regions is assigned to a tag of the set of tags based on a health metric associated with the region. The health metric is based on a bit error rate (BER), a program/erase cycle (PEC) count, a PEC condition metric, or a combination thereof. In response to selecting the first region, information is copied from the first region to a second region of the memory during the wear leveling process.

Tag-based wear leveling for a data storage device

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Xinde Hu