Cirrus Logic Inc.

Cirrus Logic International Semiconductor Limited

Xin Zhao

Xiaofan Fei

Tejasvi Das

Lei Zhu

John L Melanson

Ku He

Alan Mark Morton

Johann Guy Gaboriau

Amar Vellanki

Jing Bai

Wai-Shun Shum

Siddharth Maru

Michael Allan Kost

Matthew Beardsworth

Miao Song

John Paul Lesso

Eric Jerome King

John Bruce Bowlerwell

Saurabh Singh

Yanto Suryono

Morgan Timothy Prior

Venugopal Choukinishi

Mark James Mccloy-Stevens

Jason Lee Wardlaw

Eric J Swanson

Anthony Stephen Doy

Bruce Eliot Duewer

Thomas H Hoff

Mark May

Leyi Yin

Bradley Allan Lambert

Nishant Jain

Jun Yan

David M Olivenbaum

Vinod Jayakumar

Kemal S Demirci

Jason L Wardlaw

Wei-Shun Shum

Jeffrey Skarzynski

Ted Burk

Hossein Mirzaie

Johann G Gaboriau

Bradley A Lambert

A system may include an array of sensor elements, the array of sensor elements each comprising a first type of passive reactive element, a second type of passive reactive element electrically coupled to the array of sensor elements, a driver configured to drive the array of sensor elements and the second type of passive reactive element, and control circuitry configured to control enabling and disabling of individual sensor elements of the array of sensor elements to ensure no more than one of the array of sensor elements is enabled at a time such that when one of the array of sensor elements is enabled, the one of the array of sensor elements and the second type of passive reactive element together operate as a resonant sensor.

Single-capacitor inductive sense systems

A system may include a plurality of devices coupled to one another via a shared digital wired communication link, the plurality of devices comprising a first device configured to periodically transmit a synchronization packet onto the shared digital wired communication link to synchronize other of the plurality of devices to a reference clock of the first device, a second device configured to receive the synchronization packet and transmit one or more first data packets onto the shared digital wired communication link in response to the synchronization packet, and a third device configured to receive the synchronization packet and transmit one or more second data packets onto the shared digital wired communication link in response to the synchronization packet and the one or more second data packets.

Multi-chip synchronization in sensor applications

An audio processing system reduces perception of audible artifacts due to changes in an element in an audio channel of the audio processing system. The system reproduces an audio input signal and produces an audio output signal with the audio channel. The channel has an adjustable or selectable element that, responsive to a control signal, changes a characteristic of the audio processing channel, which generates a transient in the audio output signal. The systems include a level detector for measuring a signal level of the audio input signal and a controller responsive to an output of the level detector to determine a masking time interval available from the audio output signal due to signal content in the audio input signal. The controller generates the control signal to change the characteristic of the audio processing channel so that at least a portion of the transient occurs in the masking time interval.

Audio processing system signal-level based temporal masking

This application relates to audio driving circuitry (), and in particular to audio driving circuitry for outputting first and second audio driving signals for driving a stereo audio load (), which may be a stereo audio load of an accessory apparatus () removably coupled to the audio driving circuitry in use. A load monitor () is provided for monitoring to monitor, from a monitoring node (), an indication of a common mode return current passing through a common return path, together with an indication of a common mode component of the first and second audio driving signals and to determine an impedance characteristic of the stereo audio load. The load monitor () can provide dynamic monitoring of any significant change in load impedance. In some embodiments the load monitor () comprises an adaptive filter () which adapts a parameter of the filter which is related to the load impedance so as to determine the indication of load impedance.

Load detection

A single-inductor multiple output (SIMO) switched-power DC-DC converter for a class-D amplifier provides outputs that are symmetric about a common-mode input voltage of the amplifier, while remaining asymmetric about a return terminal of the amplifier and switching converter. The DC-DC converter includes an inductive element, a switching circuit that energizes the inductive element from an input source, and a control circuit that controls the switching circuit. The control circuit may have multiple switching modes, and in one of the multiple switching modes, the switching circuit may couple the inductive element between outputs of the converter so that stored energy produces a differential change between the voltages of the outputs. The control circuit may implement a first control loop that maintains a common mode voltage of the pair of outputs at a predetermined voltage independent of the individual voltages of the pair of outputs.

Single-inductor multiple output (SIMO) switching power supply having offset common-mode voltage for operating a class-d audio amplifier

An amplification system with an output driver stage for providing an output signal to acoustic output transducers such as speakers or haptic output devices removes signal distortion caused by output stage non-linearities by pre-distorting an input signal. The system includes the output driver stage, an input stage for receiving the input signal, and a processing block that receives the input signal and provides an output signal to the output driver stage. The processing block includes a pre-distortion circuit that applies a pre-distortion function to the input signal to generate the output signal if a signal level of the input signal is greater than a threshold amplitude, and if the signal level is less than or equal to the threshold amplitude, generates the output signal from the input signal by bypassing the pre-distortion circuit.

Signal amplitude-selected signal predistortion in an amplifier

An operational amplifier with one or more fully-differential amplifier stages has a common-mode control input. A low-frequency feedback control path is coupled between an output of the fully-differential amplifier stages and the common-mode control input to control low-frequency drift of the common-mode voltage of the output of the stages. A high-frequency feed-forward control path couples a pair of inputs of the stages to control high-frequency ripple of a common-mode voltage of the inputs of the stages. One or more of the differential amplifier stages may have a bias input that controls a direct-current (DC) bias voltage of gates of pull-up transistors of the stage that is both DC and capacitively coupled to the gates so that the stage operates with class A bias at DC and with class AB bias at high frequencies.

Frequency-selective common-mode control and output stage biasing in an operational amplifier for a class-D amplifier loop filter

A piece-wise linear (PWL) waveform generator includes a current generator that generates a reference current, an output capacitor across which an output voltage is developed to form a PWL waveform, charging and discharging current sources for charging/discharging the output capacitor based on the reference current, a clock-controlled switch network for controlling the charging/discharging of the output capacitor, and a feedback control loop that senses the output voltage and controls the current generator to vary the reference current based on the output voltage. A first switch controlled by a first clock signal periodically connects/disconnects a current source output to/from a load impedance and a second switch controlled by a second clock signal periodically connects/disconnects a capacitor to/from the current source while disconnected from the load impedance. The capacitor capacitance is based on a predetermined voltage to mitigate glitching when the first switch connects the current source output to the load impedance.

Low power high precision piecewise linear (PWL) waveform generator

A system may include a sensor having a variable phase response, a dummy impedance having a known phase response, and a measurement circuit communicatively coupled to the sensor and configured to measure first phase information associated with the sensor, measure second phase information associated with the dummy impedance, and determine a phase response of the measurement circuit based on a comparison of the first phase information to the second phase information.

Phase compensation in a resonant phase detector

A driver system may include a first n-type field-effect transistor coupled at its non-gate terminals between an output of the driver system and a first terminal of a supply voltage and configured to drive the output when the first n-type field-effect transistor is activated, a second n-type field-effect transistor coupled at its non-gate terminals between an output of the driver system and a second terminal of the supply voltage and configured to drive the output when the second n-type field-effect transistor is activated, a high-side capacitor coupled to the output of the driver system, and a low-side capacitor coupled to the second terminal of the supply voltage, wherein the high-side capacitor and the low-side capacitor are configured to track and correct for mismatches between a first resistance of the first n-type field-effect transistor and a second resistance of the second n-type field-effect transistor.

Dual bootstrapping for an open-loop pulse width modulation driver

A system may include a digital modulator configured to modulate an input signal received at an input of the digital modulator to generate a modulated input signal at an output of the digital modulator, a digital gain element having a digital gain and coupled to the digital modulator, an open-loop Class-D amplifier coupled to an output of the digital modulator and configured to amplify the modulated input signal, wherein the open-loop Class-D amplifier is powered from a variable power supply having a variable supply voltage which is variable in response to one or more characteristics of the input signal, and a control circuit configured to control the digital gain to approximately cancel changes in an analog gain of the open-loop Class-D amplifier due to variation in the variable supply voltage in response to the one or more characteristics of the input signal.

Gain control in a class-D open-loop amplifier

A digital delta-sigma modulator may include a loop filter having a loop filter input configured to receive an input signal and generate an intermediate signal responsive to the input signal and a multi-bit quantizer configured to quantize the intermediate signal into a quantized output signal which is fed back as an input to the loop filter. The multi-bit quantizer may further be configured to operate in at least two modes comprising: (a) a normal mode in which, for each sample of the intermediate signal, the multi-bit quantizer generates a corresponding sample having a value selected from a set of a plurality of quantization levels; and (b) a code suppression mode in which, for each sample of the intermediate signal, the multi-bit quantizer generates a corresponding sample having a value selected from a subset of the set of a plurality of quantization levels.

Increased noise performance using quantizer code suppression

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Austin, TX, United States of America

Xin Zhao