International Business Machines Corporation

Xin Zhang

Todd Edward Takken

Andrew Ferencz

Yuan Yao

Paul William Coteus

Meng Zhang

Hui Du

Yu Jia Tang

Yu Du

Bao Guo Xie

Shuai Zhu

Si Huang

Leland Chang

Ko-Tao Lee

Zheng Xu

Huan Hu

Qianwen Chen

Shurong Tian

Jin Ping Han

Xiaodong Cui

Naigang Wang

Dennis Merton Newns

Wen Jun Yin

Paul Michael Solomon

Robert K Montoye

Martin Ohmacht

Bruce Martin Fleischer

Yutaka Nakamura

Jeffrey Haskell Derby

Chuang Gan

Shawn Anthony Hall

Robert Matthew Senger

Rudolf Adriaan Haring

Xiaoxiao Guo

Martin Cochet

Tianyu Jia

Liam McAuliffe

Kevin Tien

Shun Zhang

Shaoze Fan

Chung-shiang Wu

An approach for reducing unwanted magnetic coupling with conductive elements by keeping the localized magnetic field in a transformer's or inductors magnetic gap far away from any conductive elements is provided. The approach includes the use of spacers to keep the localized magnetic field in a transformer's or inductor's magnetic gap far away from any conductive elements to reduce unwanted magnetic coupling with those conductive elements. The spacers can be made from materials including ferrite, conductors and non-conducting elements.

Spacer to reduce magnetic coupling

A semiconductor package provides a low profile connection to a bottom side of the semi-conductor package. The semi-conductor package includes a computer processor die and a substrate. The computer processor die is mounted on to a top surface of the substrate. The substrate is mounted on to a printed circuit board. A voltage regulator is coupled to the printed circuit board. A top surface of the voltage regulator is coupled to a bottom surface of the substrate. The package also includes a connector device. The connector device includes a cable configured to conduct power from an upstream source, and a low-profile connector module attached to an end of the cable. The connector module is configured to interface to a bottom surface of the voltage regulator.

Separable interface cable structure for high voltage under-module power input

Described aspects include a system for optimizing performance of a functional circuit unit, a method of optimizing performance of a functional circuit unit, and a computer program product. In one embodiment, the system may include a functional circuit unit having an associated cooling device and power converter, one or more sensors for the functional circuit unit, the one or more sensors including a power sensor and a temperature sensor, and a first machine learning model. The first machine learning model may be adapted to receive temperature data and power data from the one or more sensors, and to generate control signals for the cooling device and the power converter to optimize performance of the functional circuit unit.

Thermal and performance management

A method for power saving and encryption during analysis of media captured by an information capture device using a partitioned neural network includes replicating, by an information capture device, an artificial neural network (ANN) from a computer server to the information capture device. The ANN on the computer server and a replicated ANN, both, include M layers. The method further includes, in response to captured data being input to be processed, partially processing, by the information capture device, the captured data by executing a first k layers using the replicated ANN, wherein only the k layers are selected to execute on the information capture device. The method further includes transmitting, by the information capture device, an output of the k-th layer to the computer server, which partially processes the captured data by executing the remainder of the M layers using the ANN and the output of the k-th layer.

Media capture device with power saving and encryption features for partitioned neural network

Methods and systems for controlling current consumption by an electrical load of a first circuit board are described. In an example, a device of a first circuit board can measure a current being drawn by the electrical load of the first circuit board from a second circuit board. The device can generate a control signal based on a current difference between the measured current and a target current. The control signal can represent a load control parameter. The device can apply the control signal to the electrical load of the first circuit board to adjust a current consumption by the electrical load.

Current consumption controller

A broadside coupled coplanar inductor device includes first and second coplanar inductors in which the conductors of the first and second coplanar inductors are broadside coupled. The conductors are located one above the other at a first distance and the return paths are located to the side of the respective first and second conductor signal paths at a second distance. One or both of the dimensions of the first and second first distances is defined so as to maximize a mutual inductance between the conductors. First and second driver circuit apply voltages across each conductor. The input pulse width modulation signals applied to the first and second driver circuits are 180 degrees out of phase.

Broadside coupled coplanar inductors

A power converter with co-packaged secondary field effect transistors (FETs) are described. The power converter can include a first circuit, a transformer connected to an output of the first circuit, and a second circuit connected to an output of the transformer. The second circuit can include an inductor, a first FET coupled between the transformer and the inductor, and a second FET coupled between the first FET and ground. The first FET and the second FET can be co-packaged as a single package.

Power converter with co-packaged secondary field effect transistors (FETs)

A package structure is disclosed. The package structure includes processor die connected to a top surface of a package substrate. The package structure further includes a DC-DC power converter attached to a bottom surface of the package substrate. The DC-DC power converter is located at least within an open area of an interconnect component that connects the bottom surface of the package substrate and a top surface of a motherboard.

Vertical power delivery packaging structure

A system and method for supporting an interconnection of processor cores, each core with functional state monitors for monitoring operations of each processor core, the processor cores interconnected using a resistive network connected between two-terminal regions being embedded in the resistive network such that each terminal of a region may be connected by controllable resistors to one or both fixed rails or by controllable resistors to one or more intermediate nodes. The resistor values are configurable to provide indirect control of the voltages across each two-terminal region, allowing full dynamic control of voltages of the two-terminal regions in a range up to the full voltage between the two voltage rails, and where a management unit accesses the functional state monitors and controls the resistor values. Feedback from functional state monitors allow the operating frequency to extend down to arbitrarily low values and up to the limits imposed by the technology.

Stacked, reconfigurable co-regulation of processing units for ultra-wide DVFS

Embodiment of the present invention includes a magnetic structure and a magnetic structure used in a direct current (DC) to DC energy converter. The magnetic structure has an E-core and a plate, with the plate positioned in contact or in near contact with the post surfaces of the E-core. The E-core has a base, a no-winding leg, a transformer leg, and an inductor leg. The no-winding leg, the transformer leg, and the inductor leg are perpendicular and magnetically in contact with the base. The plate is a flat slab with lateral dimensions generally larger than its thickness. The plate has a plate nose that overlaps a top no-winding leg surface of the no-winding leg with a no-winding gap area to form a no-winding gap with a no-winding gap reluctance. The plate also has a plate end that overlaps a top inductor leg surface of the inductor leg with an inductor gap area to form an inductor gap with an inductor gap reluctance. In some embodiments, e.g., where the duty cycle is less than 50 percent, the inductor gap reluctance will be designed to be less than the no-winding gap reluctance. In these cases, the majority of the magnetic flux that passes through the transformer leg will return through the inductor leg, instead of through the no-winding leg. The inductor and no-winding gap reluctances can he adjusted, so that the electromotive force applied to a charge passing through the inductor will partially cancel the electromotive force applied by the transformer secondary. The gap reluctance ratio can be defined, so that the difference in secondary and inductor electromotive forces is equal to the output voltage defined by an optimal no-ripple duty cycle. In this way no changing current is required through the inductor to create a dI/dt inductive voltage drop across the output inductor. Zero output current ripple is achieved. Various embodiments of the plate, plate shape, and no-winding leg are disclosed. These embodiments allow achieving a high ratio of no-winding gap reluctance to inductor gap reluctance, for practical, affordable magnetic material structures and aspect ratios. A high gap reluctance ratio enables zero output current ripple for the high transformer turns ratios that are needed to achieve high input to output voltage ratios. The embodiments therefore allow achieving low output current ripple for 48 V or higher input voltages, 1 V or lower output voltages, and high output currents.

Magnetic cores with high reluctance differences in flux paths

Embodiments for implementing a softmax function in an analog circuit. The analog circuit may comprise a plurality of input nodes to accept voltage inputs; a plurality of diodes connected to each of the plurality of input nodes to perform a current adding function; a log amplifier coupled to the plurality of diodes; a plurality of analog adders coupled to the voltage inputs and an output of the log amplifier; and a plurality of exponential amplifiers, each of the plurality of exponential amplifiers coupled to one of the plurality of analog adders.

Analog circuit for softmax function

The structure includes a semiconductor chip connected to a substrate via one or more solder balls. The semiconductor chip includes one or more on-chip metal winding. The structure includes a first ferromagnetic core. The first ferromagnetic core is located below the semiconductor chip and above the substrate. The structure includes a second ferromagnetic core. The second ferromagnetic core is located above the semiconductor chip. The first ferromagnetic core and the second ferromagnetic core create a magnetic loop.

Semiconductor chip having one or more on-chip metal winding and enclosed by top and bottom chip-external ferromagnetic cores

The semiconductor structure includes a semiconductor-on-insulator (SOI) substrate. A group III nitride transistor is formed in a trench in the SOI substrate. The activation of the group III nitride transistor is controlled by a silicon-based transistor. The silicon-based transistor that includes a portion of a silicon layer of the SOI substrate. A group III nitride transistor device is adjacent to the silicon-based transistor.

Integrated power amplifier

A method is presented for forming a nanowire electrode. The method includes forming a plurality of nanowires over a first substrate, depositing a conducting layer over the plurality of nanowires, forming solder bumps and electrical interconnections over a second flexible substrate, and integrating nanowire electrode arrays to the second flexible substrate. The plurality of nanowires are silicon (Si) nanowires, the Si nanowires used as probes to penetrate skin of a subject to achieve electrical biopotential signals. The plurality of nanowires are formed over the first substrate by metal-assisted chemical etching.

Flexible silicon nanowire electrode

Voltage on the output terminal of an inductor is obtained as a first input signal to a control block (CB); the inductor has an input terminal connected to a power switch and driver block at a switching node. A sense input voltage is obtained on an output terminal of a sensing circuit that is not directly connected to the switching node, as a second input signal to the CB. A voltage is generated on a first output terminal of the CB and is selected such that the CB can use its first and second input signals to infer the current through the inductor. A pulse width modulation (PWM) signal is generated on a second output terminal of the CB, based on the inferred current through the inductor; the second output signal from the CB is provided to a PWM input terminal of the power switch and driver block.

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Yorktown Heights, NY, United States of America

Xin Zhang