Microsoft Technology Licensing, LLC

Hewlett-Packard Development Company, L.p.

Volterra Semiconductor Corporation

Lumileds LLC

Intersil Americas Inc.

Kinetic Technologies

Hewlett Packard Enterprise Development LP

Semiconductor Components Industries, LLC

Micro Focus Lcc

Kinetic Technologies International Holdings LP

Xin Zhang

Bruce John Sherwin, Jr

Aditya Bhandari

Anthony J Stratakos

Kaiwei Yao

Ilija Jergovic

Michael D McJimsey

Vincent W Ng

Frederic Stephane Diana

Jeroen Den Breejen

Jan Nilsson

William Robert Pelletier

Jerry Zhaolin Shan

Cipriano A Santos

Artin Der Minassians

Shailendra K Jain

Phong T Nguyen

Ivan Adrian Lopez Sanchez

Wei P Chen

Christopher G Kaler

Ludmila Cherkasova

Arun Upadhyaya Kishan

Cristian Diaconu

Pankaj Kumar

Yang Yang

Kenneth Dean Johnson

Gang Chen

Gwilym Francis Luff

Krishna Venkatraman

Jonathan E Lange

Yi Zeng

Xiaozhou Li

Kevin Michael Broas

Peter John Mole

Michael Bishop Ebersol

Jin Lin

Kay-Yut Chen

Sai Ganesh Ramachandran

Adrian Birka

Vasileios Papadimos

Wen Jia Liu

Maria Teresa Gonzalez Diaz

Hsiu-Khuem Tang

Daxin Jiang

Ryan James Ricchiuti

Weiyun Chen

Alexander Daniel Grest

Devin Leo Rider

Jose Luis Beltran Guerrero

Mayila Babang

Per-Åke Larson

Glenn W Herrick

Mark D Raper

Ming Hu

Aswinraj Govindaraj

Stephanie Sumyi Luck

Zainab Jamal

Siming Tian

Isolating resources of a virtual machine (VM) guest from a host operating system. A computer system receives an acceptance request from a guest partition corresponding to an isolated VM. The acceptance request identifies a guest memory page that is mapped into a guest physical address space of the guest partition, and a memory page visibility class. The computer system determines whether a physical memory page that is mapped to the guest memory page meets the memory page visibility class. The computer system sets a page acceptance indication for the guest memory page from an unaccepted state to an accepted state based on the physical memory page meeting the memory page visibility class.

Software isolation of virtual machine resources

The present disclosure provides method and apparatus for query conversion. A first query for a first graph database may be obtained. A syntax tree may be generated through parsing the first query. A query graph may be created based on the syntax tree. The query graph may be converted into a second query for a second graph database.

Query conversion for different graph query languages

Examples described herein relate to a system consistent with the disclosure. For instance, the system may comprise a data lake including information relating to an in-store activity of a customer and an online activity of the customer, a processing resource, and a non-transitory machine-readable medium storing instructions executable by the processing resource to identify the in-store activity and the online activity of the customer, aggregate and store the in-store activity and the online activity of the customer in the data lake, reduce an amount of products in a product portfolio, compare purchases including in-store purchases and online purchases, and recommend a product of the plurality of products based on the comparison.

Method and medium for customer product recommendations

This disclosure generally relates to enabling a hypervisor of a host machine to provide virtual interrupts to select virtual processors or a set of virtual processors. More specifically, the present disclosure describes how interrupts may be provided to targeted virtual processors, regardless of where the virtual processors are currently executing. That is, when an interrupt is received, the interrupt may be delivered to a specified virtual processor regardless of which logical processor is currently hosting the virtual processor.

Targeted interrupts for virtual processors

A system that provides intelligent constant on-time control may include a first switch coupled to a power input; a second switch coupled to the first switch; a switching node between the first switch and the second switch, the switching node configured to be connected to an inductor and a power output; feedback paths coupled to (1) a synthesized node and (2) the power output, the feedback paths enabling feedback of signals from (1) the synthesized node, and (2) the power output; and a controller coupled to the feedback paths. The controller may be configured to control a voltage at the power output based on a combination of the signals carried by the feedback paths.

Systems and methods for providing intelligent constant on-time control

This disclosure generally relates to enabling a hypervisor of a host machine to provide virtual interrupts to select virtual processors or a set of virtual processors. More specifically, the present disclosure describes how a hypervisor of a host machine may monitor the status of one or more virtual processors that are executing on the host machine and deliver interrupts to the virtual processors based on a number of factors including, but not limited to, a priority of the interrupt, a priority of the virtual processor, a current workload of the virtual processor and so on.

Interrupt management for a hypervisor

A light-emitting device comprising: a light source; and a light guide that is optically coupled to the light source, the light guide including a plurality of first non-fluorescent light extraction elements and a plurality of second non-fluorescent light extraction elements that are printed on the light guide, each of the first light extraction elements having a reflectance that is higher than a reflectance of any of the second light extraction elements, each of the first light extraction elements having a light transmittance that is lower than a light transmittance of any the second light extraction elements, each of the first light extraction elements having the same shape and size as any other one of the plurality first light extraction elements, and each of the second light extraction elements having the same shape and size as any other one of the plurality of second light extraction elements.

Light guide with patterned ink

A maximum power point tracking controller includes an input port for electrically coupling to an electric power source, an output port for electrically coupling to a load, a control switching device, and a control subsystem. The control switching device is adapted to repeatedly switch between its conductive and non-conductive states to transfer power from the input port to the output port. The control subsystem is adapted to control switching of the control switching device to regulate a voltage across the input port, based at least in part on a signal representing current flowing out of the output port, to maximize a signal representing power out of the output port.

Maximum power point tracking controllers and associated systems and methods

A system that provides intelligent constant on-time control may include a first switch coupled to a power input; a second switch coupled to the first switch; a switching node between the first switch and the second switch, the switching node configured to be connected to an inductor and a power output; feedback paths coupled to (1) the switching node and (2) the power output, the feedback paths enabling feedback of signals from (1) the switching node, and (2) the power output; and a processor coupled to the feedback paths. The processor may be configured to control a voltage at the power output based on a combination of the signals carried by the feedback paths.

This disclosure generally relates to time and timer techniques that may be used to virtualize one or more virtual machines. In an example, it may be possible to save and restore a timer of a virtual machine while preserving timer information associated with the timer (e.g., an expiration time, whether the most recent expiration has been signaled, and the enable bit, etc.). For example, a first mode may enable restoring a timer based on a previously-existing enable bit, thereby retaining the state of the timer (e.g., whether the timer is programmed to fire and/or whether the most recent expiration has been signaled). By contrast, a second mode of setting a timer may automatically set the enable bit, thereby automatically enabling the timer to fire, as may be expected by a virtual machine when setting a timer.

Hypervisors timer techniques

This disclosure generally relates to hypervisor memory virtualization. Techniques disclosed herein improve peripheral component interconnect express (PCI-e) device interoperability with a virtual machine. As an example, when a direct-memory access request is received from a PCI-e device but the target memory is currently unmapped, an indication may be provided to a memory paging processor so as to page-in the memory, such that the PCI-e device may continue to function normally. In some examples, the access request may be buffered and replayed once the memory is paged-in, or the access request may be retried, among other examples.

Hypervisor direct memory access

Speculative side channels exist when memory is accessed by speculatively-executed processor instructions. Embodiments use uncacheable memory mappings to close speculative side channels that could allow an unprivileged execution context to access a privileged execution context's memory. Based on allocation of memory location(s) to the unprivileged execution context, embodiments map these memory location(s) as uncacheable within first page table(s) corresponding to the privileged execution context, but map those same memory locations as cacheable within second page table(s) corresponding to the unprivileged execution context. This prevents a processor from carrying out speculative execution of instruction(s) from the privileged execution context that access any of this memory allocated to the unprivileged execution context, due to the unprivileged execution context's memory being mapped as uncacheable for the privileged execution context. Performance for the unprivileged execution context is substantially unaffected, however, since this memory is mapped as cacheable for the unprivileged execution context.

Speculative side channel attack mitigation using uncacheable memory

This disclosure generally relates to hypervisor memory virtualization. In an example, multiple page table stages may be used to provide a page table that may be used by a processor when processing a workload for a nested virtual machine. An intermediate (e.g., nested) hypervisor may request an additional page table stage from a parent hypervisor, which may be used to virtualize memory for one or more nested virtual machines managed by the intermediate hypervisor. Accordingly, a processor may use the additional page table stages to ultimately translate a virtual memory address for a nested virtual machine to a physical memory address.

Nested hypervisor memory virtualization

Growing community of inventors

San Jose, CA, United States of America

Xin Zhang