Xilinx, Inc.

Xin X Wu

Daniel Gitlin

Yan E Wang

Shuxian Wu

Yuhao Luo

Jae Cho

Jonathan J Ho

Michael J Hart

Mohsen Hossein Mardi

Deepak K Nayak

Shahin Toutounchi

Hong-Tsz Pan

Jae-Gyung Ahn

Hassan K Bazargan

Sheau-suey Li

Chih-Chung Wu

Bang-Thu Nguyen

Sanjiv Stokes

Shih-Liang Liang

Yohan Usthavia Frans

Jan Lodewijk De Jong

Zicheng Gary Ling

Nui Chong

Qi Lin

Jing Jing

Richard C Li

Zhi-min Ling

Jane W Sowards

Yuezhen Fan

Jonathan Jung-Ching Ho

Abu K Eghan

Hing Yee Angela Wong

Examples described herein provide for an isolation design for an inductor of a stacked integrated circuit device. An example is a multi-chip device comprising a chip stack comprising: a plurality of chips, neighboring pairs of the plurality of chips being bonded together, each chip comprising a semiconductor substrate, and a front side dielectric layer on a front side of the semiconductor substrate; an inductor disposed in a backside dielectric layer of a first chip of the plurality of chips, the backside dielectric layer being on a backside of the semiconductor substrate of the first chip opposite from the front side of the semiconductor substrate of the first chip; and an isolation wall extending from the backside dielectric layer of the first chip to the front side dielectric layer, the isolation wall comprising a through substrate via of the first chip, the isolation wall being disposed around the inductor.

Inductor design in active 3D stacking technology

An integrated circuit device layout and a method for detecting mask data handling errors are disclosed in which integrated circuit device layout includes a device region in which operable circuitry is disposed. Integrated circuit device layout also includes a verification region in which verification elements are disposed. The verification elements include cells that are duplicates of at least some of the different types of cells in device region and can include structures that are duplicates of at least some of the types of structures in the device region. The patterns in verification region are used in the final verification process to identify mask data handling errors in a mask job deck. Because the patterns in verification region are easy to locate and identify, the time required to perform the final verification process is reduced and the chance of error in the final verification process is reduced.

System and method for detecting mask data handling errors

A circuit for protecting a transistor during the manufacture of an integrated circuit device is disclosed. The circuit comprises a transistor having a gate formed over an active region formed in a die of the integrated circuit device; a protection element formed in the die of the integrated circuit device; and a programmable interconnect coupled between the gate of the transistor and the protection element, the programmable interconnect enabling the protection element to be decoupled from the transistor.

Circuit for protecting a transistor during the manufacture of an integrated circuit device

A method of protecting a transistor formed on a die of an integrated circuit is disclosed. The method comprises forming an active region of the transistor on the die; forming a gate of the transistor over the active region; coupling a primary contact to the gate of the transistor; coupling a programmable element between the gate of the transistor and a protection element; and decoupling the protection element from the gate of the transistor by way of the programmable element. Circuits for protecting a transistor formed on a die of an integrated circuit are also disclosed.

Method of and circuit for protecting a transistor formed on a die

Computer-implemented methods of generating netlists for use in post-layout simulation procedures. A lookup table includes a predetermined set of features (e.g., transistors of specified sizes and shapes) supported by an integrated circuit (IC) fabrication process, with dimensions and process induced dimension variations being included for each feature. A netlist is extracted from an IC layout, the extracted netlist specifying circuit elements (e.g., transistors) implemented by the IC layout and interconnections between the circuit elements. A search pattern is run on the IC layout to identify features in the IC layout corresponding to features included in the lookup table. Circuit elements in the extracted netlist that correspond to the identified features are then modified using values from the lookup table, and the modified netlist is output. In some embodiments, the netlist extraction, search pattern, and netlist modification are all performed as a single netlist generation step.

Methods of incorporating process-induced layout dimension changes into an integrated circuit simulation netlist

A semiconductor component having test pads and a method and apparatus for testing the same is described. In an example, an un-bumped substrate is obtained having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. In another example, a substrate is fabricated having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. An insulating layer is formed over the plurality of test pads.

Semiconductor component having test pads and method and apparatus for testing same

Method and apparatus for compensating an integrated circuit design for mechanical stress effects. One aspect of the invention relates to designing an integrated circuit. Layout data is obtained that describes layers of the integrated circuit. At least one of the layers is analyzed to detect at least one structure susceptible to damage from mechanical stress. A bias is automatically added to each of the at least one structure to reduce mechanical stress of the at least one structure as fabricated. Augmented layout data is then provided for the integrated circuit.

Method and apparatus for compensating an integrated circuit layout for mechanical stress effects

A pad pattern of a die includes first and second sets of elongated pads. The first set of elongated pads is interleaved with the second set of elongated pads. Each of the elongated pads has a bond pad area and a probe pad. Each bond pad area has a first constant width along a substantial portion thereof. Similarly, each probe pad area has a second constant width along a substantial portion thereof. The first constant width is greater than the second constant width. Each elongated pad in the first set has a first orientation. Similarly, each elongated pad in the second set has a second orientation, opposite the first orientation.

Semiconductor die with high density offset-inline bond arrangement

For IC devices that have repeating structures, a method of generating a database for making a mask layer starts with a hierarchical database describing at least one repeating element in the layer, a skeleton that surrounds the repeating elements, and instructions as to where to locate the repeating elements within the skeleton. This database is modified to generate a database that has optical proximity correction (OPC) for diffraction of light that will pass through the mask and expose photoresist on the IC layer. The optical-proximity corrected mask database is fractured by a mask house using instructions on how the modified data base will be divided to form repeating elements that are still identical after OPC, a mask skeleton that includes non-repeating elements, and instructions for placement of the repeating elements in the skeleton. Thus the resulting mask database is smaller than a mask database that includes all copies of repeating elements.

Method of generating an IC mask using a reduced database

An ESD protection circuit includes a bipolar transistor, a resistor, and a zener diode formed on and within a semiconductor substrate. The resistor extends between the base and emitter regions of the transistor so that voltage developed across the resistor can turn on the transistor. The zener diode is formed in series with the resistor and extends between the base and collector regions of the transistor. Thus configured, breakdown current through the zener diode, typically in response to an ESD event, turns on the transistor to provide a nondestructive discharge path for the ESD. The zener diode includes anode and cathode diffusions. The cathode diffusion extends down into the semiconductor substrate in a direction perpendicular to the substrate. The anode diffusion extends down through the cathode diffusion into the semiconductor substrate. The anode diffusion extends down further than the cathode diffusion so that the zener diode is arranged vertically with respect to the substrate. The cathode diffusion can be formed using two separate diffusions, one of which extends deeper into the substrate than other.

Method of forming a zener diode

A reticle (mask) that is modified to prevent bridging of the masking material (e.g., chrome) between long mask lines of a lithographic mask pattern during an integrated circuit fabrication process. A dummy mask pattern is provided on the reticle adjacent to long mask lines that causes the large charge collected on the long mask line to be distributed along its length, thereby minimizing voltage potentials across a gap separating the long mask line from an adjacent mask line.

Methods and structures for protecting reticles from electrostatic damage

A reticle that is modified to prevent bridging of the masking material (e.g., chrome) between portions of the lithographic mask pattern during an integrated circuit fabrication process. According to a first aspect, the modification involves electrically connecting the various portions of the lithographic mask pattern that balance charges generated in the portions during fabrication processes. In one embodiment, sub-resolution wires that extend between the lithographic mask pattern portions facilitate electrical conduction between the mask pattern portions, thereby equalizing dissimilar charges. In another embodiment, a transparent conductive film is formed over the lithographic mask pattern to facilitate conduction. In accordance with a second aspect, the modification involves separating the various portions of the lithographic mask pattern into relatively small segments by providing sub-resolution gaps between the various portions, thereby minimizing the amount of charge that is generated on each portion.

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Fremont, CA, United States of America

Xin X Wu