Chartered Semiconductor Manufacturing Ltd (Corporation)

Globalfoundries Singapore Pte. Ltd.

Asm Technology Singapore Pte Ltd

Xin Wei Zhang

Carol Goh

Mei Sheng Zhou

Pradeep Yelehanka

Hai Cong

Keng Yew Song

Soon Ee Neoh

Kin Wai Tang

Yi Bin Wang

Wai Wah Lee

Yat Meng Ng

Wen Hua Guo

Wei Loong Loh

Aik Hon Goh

Krishan Gopal

Guat Choo Goh

A capillary is utilized to form the wedge wire bond comprised in a wire interconnection. A wire holding device is located above a wire clamp and the capillary to secure the wire while the wire clamp is open and not clamping onto the wire. The wire clamp and the capillary may be lifted relative to the wire in a direction away from the wedge wire bond and towards the wire holding device so as to pay out a length of wire from the capillary. At a predetermined height of the capillary, the wire clamp is closed to clamp onto the wire, and thereafter, the capillary and wire clamp may be moved further away from the wedge wire bond to cause the wire to break away from the wedge wire bond and to form the wire tail with a desired length extending from the capillary.

Automatic wire tail adjustment system for wire bonders

A method for forming device features with reduced line end shortening (LES) includes trimming the device feature to achieve the desired sub-ground rule critical dimension during the etch to form the device feature.

Processing with reduced line end shortening ratio

A two step passivation procedure, used to remove chlorine from polymer layers formed on the sides of metal structures, prior to removal of the defining photoresist shape, and of the polymer layers, has been developed. The procedure features a first passivation step, performed at a low substrate temperature, (100-140&deg; C.) at low RF power, (150 to 250 watts), and using a 2 to 1 ratio of oxygen to water, resulting in removal of corrosion causing chlorine, from the polymer layers, located on the sides of a first group of defined metal structures, which in turn reside at the edge of a semiconductor substrate. A second passivation step, of the two step passivation procedure, is then performed using water only, at higher substrate temperature, (200-250&deg; C.), resulting in removal of chlorine from polymer layers located on the sides of a second set of metal structures, which reside at the center of the semiconductor substrate. Removal of the masking photoresist shape, and removal of the polymer layers, now without chlorine, is then performed.

Enhanced passivation scheme for post metal etch clean process

In one embodiment, a spacer layer (,) is formed overlying a gate electrode (,), which is formed on a semiconductor substrate (,). The spacer layer (,) is then etched to form a sidewall spacer (,). A scanning electron microscope (SEM) is then used to measure the width of the sidewall spacer (,). The measured value for the width of the sidewall spacer (,) is then used to adjust a subsequent integrated circuit fabrication process, such as a spacer etch process, an implant process, or an anneal process. As a result, transistors with improved drain saturation currents are fabricated.

Method for forming a transistor within an integrated circuit

A process for forming aluminum based interconnect structures, with a reduced risk of void formation, occurring during photoresist removal and clean up procedures, has been developed. The process features removing the photoresist layer, used as a mask for patterning of an aluminum based layer, using a two phase, in situ photoresist removal procedure, followed by a cold water rinse. An aluminum oxide layer, formed during the initial phase of the two phase, in situ photoresist removal procedure, protects the sides of the aluminum based interconnect structure, during post-clean procedures, reducing the risk of galvanic corrosion and void formation. In addition the temperature of a DI water, post-clean procedure, has also been decreased to between about 5 to 10.degree. C., reduced, also reducing the risk of galvanic corrosion, that can occur during the post clean procedures.

Elimination of void formation in aluminum based interconnect structures

A new method of removing photoresist residues and sidewall deposits is described. Semiconductor device structures are provided in and on a semiconductor substrate. The semiconductor device structures are covered with an insulating layer. A metal layer is deposited overlying the insulating layer. The metal layer is covered with a layer of photoresist. The photoresist layer is exposed to actinic light and developed and patterned to form the desired photoresist mask. The metal layer is etched away where it is not covered by the photoresist mask to form metal lines whereby a photoresist residue remains overlying the metal lines and whereby sidewall deposits form on the sidewalls of the metal lines. The wafer is exposed to a plasma comprising O.sub.2 and CF.sub.4 at a low power of less than about 200 watts whereby an upper portion of the photoresist residue and a portion of the sidewall deposits are removed. Thereafter, the wafer is heated and then rinsed whereby all of the sidewall deposits are removed. Thereafter, the wafer is exposed to oxygen ashing whereby all of the photoresist residue is removed.

Dark CF.sub.4 flash

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Singapore, Singapore

Xin Wei Zhang