Applied Materials, Inc.

Advanced Micro Devices Corporation

Spansion LLC.

Xin Sheng Guo

Zhigang Wang

Nian Niles Yang

Richard M Fastow

Jun Zhao

Tom K Cho

Lawrence C Lei

Mohan K Bhan

Alex Schreiber

John M White

Ling Chen

John JianShi Wang

Kevin P Fairbairn

Yue-Song He

Bo Zheng

Charles N Dornfest

Stefan A Wolff

Keith K Koai

John C Egermeier

Mark A Mueller

Shin-Hung Li

Mei Yin Chang

Sameer S Haddad

Avi Tepman

Tien-Chun Yang

Ashok K Sinha

Darlene G Hamilton

Anand Gupta

Virendra V Rana

Jianmin Qiao

Ken Cheong Cheah

John Vincent Schmitt

Kendra Nguyen

Virendra V S Rana

Sheung-Hee Park

Russell C Ellwanger

Shih-Hung Li

Mimi Lee

Soonil Hong

Michael Achter

Atsushi Tabata

Andrew Conners

Justin Jones

A method is discussed for providing programmable test conditions for a built-in self test circuit of a flash memory device. The method comprises providing a BIST interface adapted to adjust a test condition used in a BIST circuit, providing the memory cells of the Flash memory device, and providing the BIST circuit adapted to test the flash memory. The method further comprises communicating with the BIST interface one or more global variables associated with the test condition, adjusting the test condition used by the BIST circuit based on the values represented by the global variables, performing one or more test operations on the flash memory in accordance with the adjusted test condition, and reporting the results of the memory test operations. The method of the present invention may further include a serial communications medium and the use of a serial test protocol for communicating the global variables to the BIST interface and test results from the interface. The global variables may also be provided by a memory device user.

Automated tests for built-in self test

A low power charge pump is disclosed. A pump driving node of a first pump stage is selectively coupled to a pump driving node of the subsequent pump stage. Subsequent to a transfer of charge from a first pump stage to a subsequent stage, the first and subsequent pump driving nodes are coupled. Residual charge on a first stage pump driving node is thereby transferred to a subsequent pump driving node. Subsequent to the transfer of charge from the first pump driving node to the second pump driving node, the nodes are uncoupled. By selectively coupling a first pump stage to a pump driving node of the subsequent pump stage, the first pump driving node may pre-charge the subsequent pump driving node, thereby reducing the energy that must be provided by clock driving circuitry to produce a positive-going transition of a driving clock. Advantageously, pre-charging energy is taken from the first stage, reducing the energy that was heretofore dissipated by clock driving circuitry during a negative-going clock signal transition. In this novel manner conversion efficiency of a charge pump device may be beneficially increased, providing enhanced low power performance.

Low power charge pump

A method for standard reference cell design is herein disclosed. The method includes determining a first number of individual bits to be employed in a standard reference cell design based on the number of individual bits that are included in core memory cells that are to be measured using the standard reference cell. The method further includes determining a range of variation in the core memory cells to be measured that is due to process variation in the generation of the core memory cells. In addition, the method includes determining an additional number of individual bits to be included in the standard reference cell design based on the determined range of variation. A standard reference cell that includes a number of individual bits equal to the sum of both the first and the additional number of individual bits is generated.

Method of reference cell design for optimized memory circuit yield

A process technology effectuates production of low defect homogeneous oxynitride, which can be applied in tunneling dielectrics with high dielectric constants and low barrier heights for flash memory devices, and as gate oxide for ultra-thin logic devices. The process technology involves varying the oxygen content in a the homogeneous oxynitride film comprising a part of the flash memory device, which effectively increases the dielectric constant of the oxynitride film and lowers its barrier height. In one such process, a controlled co-flow of NO is introduced into a CVD deposition process. This process effectuates production of a oxynitride film with uniform distributions of nitrogen and oxygen throughout.

Method for producing a low defect homogeneous oxynitride

A method and system for reading flash memory. A leakage current of a common bit line comprising the flash memory cell is accessed. A read current of the flash memory cell is accessed. The leakage current is eliminated from the read current to determine a cell current. The cell current is compared to an erase verify cell current. The currents may be directly subtracted, or they may be converted to corresponding voltages and the voltages subtracted. Advantageously, cells may be correctly verified for erasure without a preliminary search and recovery of over erased bits. As a beneficial result, the search and recovery of over erased bits does not need to be performed during an erase process. Advantageously, such steps may be eliminated from an erase process, recovering the time otherwise required to perform such steps, and thereby speeding up the erase process.

Reading flash memory

A charge pump oscillator circuit with compensation for variations in process and operating environment. The charge pump oscillator is designed with a rolloff characteristic that enables operation at both weak and strong process corners without excessive power consumption. Composite resistors in the oscillator circuit are composed of component resistors that are fabricated with different processes, e.g., implant and deposition. The resistance of the composite resistor is thus in order to provide compensation for variations in processing and operating environment. The composite resistor may be used as a feedback loop resistor, or may be used as a source degenerate resistor to control the supply current to the oscillator.

Compensated oscillator circuit for charge pumps

A method and system for improving short channel effect on a floating gate device is disclosed. In one embodiment, a p-type implant is applied to a source side of the floating gate device. In addition, the present embodiment applies a p-type implant to a drain side of the floating gate device. The p-type implant to the drain side is performed at a different angle than the p-type implant to the source side. The p-type implant to the drain side is implanted to a greater depth than that of the p-type implant to the source side.

Method and system for improving short channel effect on a floating gate device

A method for detecting tunnel oxide encroachment on a memory device. In one method embodiment, the present invention applies a baseline voltage burst to a gate of the memory device. Next, the present embodiment generates a baseline performance distribution graph of bit line current as a function of gate voltage for the memory device. The present embodiment then applies a channel program voltage burst to the gate of the memory device. Moreover, the present embodiment generates a channel program performance distribution graph of bit line current as a function of gate voltage for the memory device. The present embodiment then applies a channel erase voltage burst to the gate of the memory device. Additionally, the present embodiment generates a channel erase performance distribution graph of bit line current as a function of gate voltage for the memory device. A comparison of the channel program performance distribution graph and the channel erase performance distribution graph with respect to said baseline performance distribution graph is then performed. In so doing, an asymmetric distribution of the channel program performance distribution graph and the channel erase performance distribution graph with respect to the baseline performance distribution indicates tunnel oxide encroachment.

Method and system for detecting tunnel oxide encroachment on a memory device

A memory device with homogeneous oxynitride tunneling dielectric. Specifically, the present invention describes a flash memory cell that includes a tunnel oxide dielectric layer including homogeneous oxynitride. The tunnel oxide dielectric layer separates a floating gate from a channel region that is formed between a source region and a drain region in a substrate. The flash memory cell further includes a dielectric layer that separates a control gate from the floating gate. In one case, the homogenous oxynitride is a defect free silicon nitride. The homogeneity of the oxynitride is due to the uniform distribution of nitride within the tunnel oxide dielectric layer. Further, the use of the homogeneous oxynitride can increase the dielectric constant and lower the barrier height of the tunnel oxide dielectric layer for increased performance. Also, the homogenous oxynitride supports source-side channel hot hole erasing in the flash memory cell.

Floating gate memory device with homogeneous oxynitride tunneling dielectric

A method of semiconductor integrated circuit fabrication. Specifically, one embodiment of the present invention discloses a method for reducing shallow trench isolation (STI) corner recess of silicon in order to reduce STI edge thinning for peripheral thin gate transistor devices in an integrated circuit comprising flash memory devices and both thick and thin gate transistor devices. The method begins by forming a tunnel oxide layer over a semiconductor substrate for the formation of the flash memory devices (step ). A mask is formed over the thin gate transistor devices to inhibit formation of a thick gate oxide layer for the formation of the thick gate transistor devices (step ). The mask reduces shallow trench isolation (STI) recess by eliminating removal of the thick gate oxide layer before forming a thin oxide layer for the thin gate transistor devices

Method for reducing shallow trench isolation edge thinning on thin gate oxides to improve peripheral transistor reliability and performance for high performance flash memory devices

A method and apparatus for testing semiconductors comprising stacked floating gate structures. A floating gate is programmed ( ). An electrical stress or disturb voltage is applied to a control gate with a source and a drain in a specific set of conditions ( ). Subsequent to the stressing, a drain current versus gate voltage relationship is measured ( ). The sequence of programming, stressing and measuring may be repeated ( ) with different conditions for source and drain. More particularly, positive and negative biases are applied to a source while a drain is held at ground, and similar biases are applied to a drain while a source is held at ground. Through inspection of the measurement information taken after this sequence of stress applications, a stack gate edge-defect may be identified ( ) as associated with a source edge or a drain edge. In this novel manner, stack gate edge defects may be identified and localized via non-destructive means, and corrective actions to the semiconductor manufacturing process and/or the partially manufactured wafer may be taken.

Method of detecting and distinguishing stack gate edge defects at the source or drain junction

According to one embodiment, the memory circuit comprises a memory sector having a plurality of memory cells. Each of the plurality of memory cells has a gate connected to a corresponding word line, where each corresponding word line is further connected to an output of a corresponding decoding circuit. Each corresponding decoding circuit receives a corresponding vertical word line signal, a corresponding global word line signal, and a corresponding sector supply voltage. The corresponding sector supply voltage is capable of supplying an erase voltage, such as &minus;9 V for a negative gate erase memory device, for example. With this arrangement, the corresponding decoding circuit is capable of selectively excluding the corresponding word line from receiving the erase voltage during the erase operation.

Memory circuit for providing word line redundancy in a memory sector

The present invention generally relates to a method of determining a source/drain junction overlap and a channel length of a small device, such as a MOS transistor. A large reference device having a known channel length is provided, and a source, drain, and substrate on which the device has been formed are grounded. A predetermined gate voltage is applied to a gate of the large device, and a gate to channel current of the reference device is measured. A source, drain, and substrate on which the small device has been formed are grounded, and the predetermined voltage is applied to a gate of the small device, and a gate to channel current of the small device is measured. The substrate and one of the source or the drain of the small device is floated, and a predetermined drain voltage is applied to source or the drain which is not floating. A gate to drain current for the small device is measured, and a source/drain junction overlap length is calculated. The source/drain junction overlap length is then used to calculate the channel length of the small device.

Extraction of drain junction overlap with the gate and the channel length for ultra-small CMOS devices with ultra-thin gate oxides

A floating gate flash memory device including a substrate comprising a source region, a drain region, and a channel region positioned therebetween; a floating gate electrode positioned above the channel region and separated from the channel region by a tunnel dielectric material layer; and a control gate electrode positioned above the floating gate electrode and separated from the floating gate electrode by an interpoly dielectric layer, the interpoly dielectric layer comprising a modified ONO structure having a bottom dielectric material layer adjacent to the floating gate electrode, a top dielectric material layer adjacent to the control gate electrode, and a center layer comprising a nitride and positioned between the bottom dielectric material layer and the top dielectric material layer, in which the tunnel dielectric material layer, and at least one of the bottom dielectric material layer and the top dielectric material layer, comprise a high-K dielectric material.

Use of high-K dielectric material for ONO and tunnel oxide to improve floating gate flash memory coupling

Methods are disclosed for determining tunnel oxide reliability of flash memory devices in a wafer prior to sorting and packaging without damaging or stressing the devices. The methods comprise measuring an initial threshold voltage of a test cell having the same tunnel oxide as other flash cells on the wafer, applying an erase stress to the test cell for a first time period and a program stress to the test cell for a second time period, and measuring the final threshold voltage of the test cell. The difference between the initial and final threshold voltages is then used to determine or estimate the tunnel oxide reliability of the flash memory cells on the wafer.

Methods and systems for flash memory tunnel oxide reliability testing

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Los Altos Hills, CA, United States of America

Xin Sheng Guo