Apple Inc.

Xin Miao

Emre Alptekin

Saurabh P Sinha

Shahzad Nazar

A memory device layout that implements SRAM cells with stacked transistors is disclosed. The memory utilizes both topside metal routing and backside metal routing for routing of bitlines between bit cells with stacked transistors and logic cells coupled to the bit cells.

SRAM macro design architecture

A SRAM cell layout that implements stacked transistors is disclosed. The cell layout utilizes both topside metal routing and backside metal routing along with stacked transistors to provide multiple transistors for implementation of inverters and pass gates in a memory cell. Various connection routes between components of the transistors (e.g., gates, sources, and drains) are made to allow cross-coupling between inverters in the memory cell.

Stacked SRAM cell architecture

Device layouts for integrated circuit devices that include threshold voltage shift induced by placement of alternate work function metals adjacent active gates are disclosed. The device layouts include a single epitaxy for active regions in the device with common source/drain regions among the active region rows in the layouts. Metal gate sections above one or more rows of active regions may be replaced with metal of a different work function in inactive regions of the layout. The different work function metal in the inactive regions will induce threshold voltage shift in adjacent (neighboring) active transistors of the device layouts.

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Saratoga, CA, United States of America

Xin Miao