International Business Machines Corporation

Globalfoundries Inc.

Adeia Semiconductor Bonding Technologies Inc.

Elpis Technologies Inc.

Xin Miao

Kangguo Cheng

Chen Zhang

Wenyu Xu

Alexander Reznicek

Juntao Li

Jingyun Zhang

Michael A Guillorn

Tenko Yamashita

Ruilong Xie

Isaac Lauer

Bruce Bennett Doris

Nicolas J Loubet

Choonghyun Lee

Zhenxing Bi

Peng Xu

Josephine B Chang

Zuoguang Liu

Chun-chen Yeh

Heng Wu

Sanjay C Mehta

Philip Joseph Oldiges

Ramachandra Divakaruni

Terence B Hook

Darsen D Lu

Veeraraghavan S Basker

Junli Wang

Shogo Mochizuki

Lan Yu

Bruce Miao

Balasubramanian Pranatharthiharan

Richard Glen Southwick, Iii

Brent A Anderson

Takashi Ando

Hemanth Jagannathan

Ruqiang Bao

Su Chen Fan

Steven J Bentley

Joshua M Rubin

Richard Anthony Conti

Chun Wing Yeung

Pierre Morin

Jody Alan Fronheiser

Yi Song

Catherine B Labelle

Kisup Chung

ChoongHyun Lee

Terry Hook

Joseph S Washington

A nanosheet device includes a bottom dielectric isolation formed by a first portion of a high-k dielectric layer above a semiconductor substrate, a spacer material above the first portion of the high-k dielectric layer and a second portion of the high-k dielectric layer above the spacer material. A sequence of semiconductor channel layers are stacked perpendicularly to the semiconductor substrate above the bottom dielectric isolation and are separated by and vertically aligned with a metal gate stack. Source/drain regions extend laterally from opposite ends of the semiconductor channel layers with a bottom surface of the source/drain regions being in direct contact with the bottom dielectric isolation for electrically isolating the source/drain regions from the semiconductor substrate.

Nanosheet device with tri-layer bottom dielectric isolation

Vertical transport field-effect transistors are formed on active regions wherein the active regions each include a wrap-around metal silicide contact on vertically extending side walls of the active region. Such wrap-around contacts form self-aligned and reliable strapping for SRAM bottom nFET and pFET source/drain regions. Buried contacts of SRAM cells may be used to strap the wrap-around metal silicide contacts with the gates of inverters thereof. Wrap-around metal silicide contacts provide additional contacts for logic FETs and reduce parasitic bottom source/drain resistance.

Vertical transport field-effect transistor with ring-shaped wrap-around contact

A semiconductor structure includes a plurality of fins on a semiconductor substrate, the plurality of fins including an alternating sequence of a first nanosheet made of epitaxially grown silicon and a second nanosheet made of epitaxially grown silicon germanium, and a shallow trench isolation region within the semiconductor substrate adjacent to the plurality of fins. The shallow trench isolation region including a recess within the substrate filled with a first liner, a second liner directly above the first liner, a third liner directly above the second liner, and a dielectric material directly above the third liner. The first liner is made of a first oxide material, the third liner is made of a nitride material, and the second liner is made of a second oxide material that creates a dipole effect for neutralizing positive charges within the third liner and positive charges between the third liner and the first liner.

Tri-layer STI liner for nanosheet leakage control

A vertical field-effect transistor includes a substrate comprising a semiconductor material; a first set of fins formed from the semiconductor material and extending vertically with respect to the substrate; and a second set of fins extending vertically with respect to the substrate, wherein ones of the second set of fins abut ones of the first set of fins. The second set of fins comprises a dielectric material.

Vertical field-effect transistor with dielectric fin extension

A method for manufacturing a semiconductor device includes forming a source layer on a semiconductor substrate, forming a channel layer on the source layer, and forming a drain layer on the channel layer. The source, channel and drain layers are patterned into at least one fin, and a cap layer is formed on a lower portion of the at least one fin. The lower portion of the at least one fin includes the source layer and part of the channel layer. The method further includes forming a gate structure comprising a gate dielectric layer and a gate conductor on the at least one fin and on the cap layer. The cap layer is positioned between the lower portion of the at least one fin and the gate dielectric layer.

Tunnel field-effect transistor with reduced subthreshold swing

Devices and methods are provided for forming single diffusion break isolation structures for integrated circuit devices including gate-all-around FET devices such as nanosheet FET devices and nanowire FET devices. For example, a semiconductor integrated circuit device includes first and second gate-all-around field-effect transistor devices disposed in first and second device regions, respectively, of a semiconductor substrate. A single diffusion break isolation structure is disposed between the first and second device regions. The single diffusion break isolation structure includes a dummy gate structure disposed on the semiconductor substrate between a first source/drain layer of the first gate-all-around field-effect transistor device and a second source/drain layer of the second gate all-around field-effect transistor device. The single diffusion break isolation structure is configured to electrically isolate the first and second source/drain layers.

Single diffusion break isolation for gate-all-around field-effect transistor devices

A method of fabricating a semiconductor device is described. The method includes forming a nanosheet stack on a substrate, the nanosheet stack includes nanosheet channel layers. A gate is formed around the nanosheet channel layers of the nanosheet stack. A strained material is formed along a sidewall surface of the gate. The strained material is configured to create strain in the nanosheet channel layers of the nanosheet stack.

Nanosheet transistors with strained channel regions

A semiconductor device including a plurality of nanosheet transistor channels adjacent to a source/drain. An inner spacer located between each of the plurality of nanosheet transistor channels and the inner spacer wraps around the end of each of the plurality of nanosheet transistors. The source/drain is in contact with the inner spacer and each of the plurality of nanosheet transistor channels. A gate surrounding each of the plurality of nanosheet transistor channels and an electrical contact connected to the source/drain. An ultra low-k spacer located between the gate and the source/drain. The ultra low-k spacer reduces the parasitic capacitance of the nanosheet transistor.

Nanosheet transistor with ultra low-k spacer and improved patterning robustness

The subject disclosure relates to high mobility complementary metal-oxide-semiconductor (CMOS) devices and techniques for forming the CMOS devices with fins formed directly on the insulator. According to an embodiment, a method for forming such a high mobility CMOS device can comprise forming, via a first epitaxial growth of a first material, first pillars within first trenches formed within a dielectric layer, wherein the dielectric layer is formed on a silicon substrate, and wherein the first pillars comprise first portions with defects and second portions without the defects. The method can further comprise forming second trenches within a first region of the dielectric layer, and further forming second pillars within the second trenches via a second epitaxial growth of one or more second materials using the second portions of the first pillars as seeds for the second epitaxial growth.

Method of forming high mobility complementary metal-oxide-semiconductor (CMOS) devices with fins on insulator

A method of forming a vertical fin field effect transistor device is provided. The method includes forming a vertical fin and fin template on a bottom source/drain layer, wherein the fin template is on the vertical fin. The method further includes forming a gate structure on the vertical fin and fin template, and forming a top spacer layer on the gate structure. The method further includes removing the fin template to form an opening in the top spacer layer, and removing a portion of a gate electrode of the gate structure to form a cavity; and removing a portion of a gate dielectric layer of the gate structure to form a groove around the vertical fin.

Vertical transistor devices with composite high-K and low-K spacers with a controlled top junction

A method of forming a vertical fin field effect device is provided. The method includes, forming a vertical fin on a substrate, forming a masking block on the vertical fin, wherein the masking block extends a distance outward from the vertical fin sidewalls and endwalls, and a portion of the substrate surrounding the masking block is exposed. The method further includes removing at least a portion of the exposed portion of the substrate to form a recess and a fin mesa below the vertical fin, removing a portion of the fin mesa to form an undercut recess below an overhanging portion of the masking block, forming a spacer layer on the masking block and in the undercut recess, and removing a portion of the spacer layer to form an undercut spacer in the undercut recess.

Vertical fin field effect transistor with a reduced gate-to-bottom source/drain parasitic capacitance

A method of manufacturing a nanosheet field effect transistor (FET) device is provided. The method includes forming a plurality of nanosheet stacks on a substrate, the nanosheet stacks including alternating layers of first type sacrificial layers and active semiconductor layers. The method includes forming the first type sacrificial layer on sidewalls of the nanosheet stacks, then forming a dielectric pillar between the sidewall portions of the first type sacrificial layers of adjacent nanosheet stacks, and then removing the first type sacrificial layer. The method also includes forming a PWFM layer in spaces formed by the removal of the first type sacrificial layer for a first one of the nanosheet stacks, and includes forming a NWFM layer in spaces formed by the removal of the first type sacrificial layer for an adjacent second one of the nanosheet stacks.

Nanosheet semiconductor devices with n/p boundary structure

A method for fabricating a stacked nanopore includes forming a stack of layers having alternating conductive lines and dielectric layers on a substrate, and patterning the stack to form a staircase structure with the conductive lines having a length gradually changing at each level in the stack. The method also includes depositing and planarizing a dielectric material over the staircase structure, forming contacts through the dielectric material to the conductive lines for each level of conductive lines, etching a nanopore through the stack of layers to form pairs of opposing electrodes across the nanopore using the conductive lines; and opening up the substrate to expose the nanopore.

DNA sequencing with stacked nanopores

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Xin Miao