Parade Technologies, Ltd.

Xin Jin

Ming Qu

Zhengyu Yuan

Qing Yu

YingFan Lee

Andrew Lee

Zhih-Ling Lu

A method controls duty cycle distortion of clock signals. An electronic device obtains an input clock signal having a first frequency and a sampling clock signal having a second frequency that is lower than the first frequency. The sampling clock signal has a random noise distribution. The sampling clock signal is applied to sample high voltage duty cycles and low voltage duty cycles of the input clock signal for a duration of time to obtain a sampling result. The electronic device determines a duty cycle distortion level of the input clock signal in the duration of time based on the sampling result. A duty cycle control signal is generated based on the duty cycle distortion level to control the high voltage duty cycles of the input clock signal.

Controlling duty cycle distortion with digital circuit

Controlling Duty Cycle Distortion with a Mixed-Signal Circuit A method controls the duty cycle distortion of clock signals. An electronic device obtains an input clock signal and generates a first output voltage and a second output voltage from the input clock signal. The first output voltage has a first direct current (DC) voltage level indicating, in real time, a first duty cycle length of high voltage duty cycles of the input clock signal. The second output voltage has a second DC voltage level indicating, in real time, a second duty cycle length of low voltage duty cycles of the input clock signal. The difference between the first and second DC voltage levels corresponds to the duty cycle distortion level of the input clock signal. A duty cycle control signal is generated based on the difference between the first and second DC voltage levels to control the high voltage duty cycles of the input clock signal.

Controlling duty cycle distortion with a mixed-signal circuit

A system and method are disclosed to control the power consumption of column drivers in a display system. A video input signal is received which has an active video period and a vertical blanking period between frames. A timing controller transmits a first video frame to a column driver. The timing controller transmits a column driver disable command during a vertical blanking period. Prior to the subsequent active video period, the timing controller transmits a column driver enable command. The timing controller proceeds to transmit a second video frame to the column driver. In one embodiment, the timing controller determines whether to disable and enable the column driver based on a refresh rate, the refresh rate calculated by the timing controller from the video input signal.

Power reduction technique for digital display panel with point to point intra panel interface

A system and method are disclosed for embedding a timing controller on column drivers which, among other advantages, reduces power consumption and size constraints. A standalone timing controller is eliminated by splitting a video input signal and delivering the signal to each of the column drivers. Timing controller functionality is embedded in each of the column drivers to allow the column drivers to process the received video signal. An auxiliary input used for communication between column drivers and an external system is received by a master column driver. The master column driver communicates with slave column drivers to enable point to point communication between each column driver and the external system.

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San Jose, CA, United States of America

Xin Jin