Intel Corporation

Sk Hynix Nand Product Solutions Corp.

Microchip Technology Inc.

Xin Guo

Yogesh B Wakchaure

David J Pelster

Aliasgar S Madraswala

Hanmant Pramod Belgal

Kiran Pangal

Robert Frickey

Donia Sebastian

David B Carlton

Pranav Kalavade

Paul D Ruby

Feng Zhu

Ning Wu

Mark Anthony Golez

Ali Khakifirooz

Iwen Chao

Yu Du

Neelesh Vemula

Eric L Hoffman

Qingru Meng

Lei Chen

Kristopher H Gaewsky

Scott Nelson

Lark-Hoon Leem

Ryan J Norton

Jawad Basit Khan

Ravi H Motwani

Wei Wu

Neal R Mielke

Yi Zou

Myron Loewen

Sagar Upadhyay

Purval Shyam Sule

Hiroyuki Sanda

Curtis A Gittens

Brennan A Watt

Krishna Kumar Parat

Mase J Taub

Andrew W Vogan

Shantanu R Rajwade

Ravi J Kumar

Ye Zhang

Rohit Sudhir Shenoy

Sai Krishna Mylavarapu

Ihab Jaser

Shyam Sunder Raghunathan

Ramkarthik Ganesan

Naveen Prabhu Vittal Prabhu

Robert E Frickey

Jack Wynne

Kyung Jean Yoon

Joseph F Doller

David M Jones

Cole Uhlman

Ivan Kalastirsky

Varsha Regulapati

Joel T Jorgensen

Naga Kiranmayee Upadhyayula

Sagar S Sidhpura

Kwok Kong

Solomon Sagar Albert Jayaraj

Aaron Lutzker

Fnu Sachin

Justin R Dayacap

Rosanna Yee

Svanhild M Salmons

Chu-hsiang Teng

Kaoru Naganuma

Jing-Jing Li

Shu-Jen Lee

An apparatus and method for scheduling memory requests including receiving a plurality of requests having a type and associating each request of the received plurality of requests with a corresponding target, which is associated with one channel of a plurality of channels. The method assigning a priority to each request, assigning a utilization cost to each request based on the request's target and request type, and queueing each request of the plurality of requests for scheduling. The method selecting a first request of the received plurality of requests to be scheduled based on its priority, scheduling the first request for processing at a time when the first request utilization cost is less than or equal to a current value of a dynamic utilization counter, and debiting the dynamic utilization counter by the first request utilization cost.

System and method for centralized management of workload and parallel service of prioritized requests

Systems, apparatuses and methods provide for a memory controller to manage quality of service enforcement. For example, a memory controller includes logic to determine a plurality of projected bandwidth levels and a plurality of projected quality of service levels on a user-by-user basis. The projected bandwidth levels and the projected quality of service levels are determined for a plurality of device configurations based on one or more storage device parameters. A requested bandwidth level and a requested quality of service level is received from a host in response to the plurality of projected bandwidth levels and the plurality of projected quality of service levels.

Managing quality of service by allocating die parallelism with variable queue depth

A method performed by a solid state drive is described. The method includes, on a channel that internally couples a controller of the solid state drive to a storage device of the solid state drive, sending write data for a program operation to be performed by one of the storage device's logical units in separate chunks over the channel. The method also includes inserting higher priority traffic items of other logical units of the storage device in between the separate chunks.

Solid state drive with multiplexed internal channel access during program data transfers

Systems, apparatuses and methods may provide for technology that generates a first set of scrambler bits based on a destination page number associated with data, generates a second set of scrambler bits based on a programmable nonlinear function, and combines the first set of scrambler bits and the second set of scrambler bits into a scrambler seed. In one example, the technology also randomizes the data based on the scrambler seed to obtain outgoing randomized data and writes the outgoing randomized data to a non-volatile memory.

Programmable and high-performance data scrambler for non-volatile memory controllers

A method and apparatus to reduce read retry operations in a NAND Flash memory is provided. To reduce the number of read retries for future reads, a word line group is assigned an optimal read voltage, the reference voltage that results in eliminating the read error for the word line is selected as the optimal read voltage (also referred to as a 'sticky voltage') for the word line group to be used for a next read of the page. An optimal read voltage per word line group for the page per NAND Flash memory die is stored in the lookup table. Storing an optimal read voltage per word line group instead of per die reduces the number of read retries.

Method and apparatus to improve read latency of a multi-threshold level cell block-based non-volatile memory

An apparatus is described. The apparatus includes a memory chip having logic circuitry to suspend application of an erasure voltage, wherein, respective responses of the erasure voltage to a decision to suspend the application of the erasure voltage depend on where the erasure voltage is along its waveform.

Solid state drive (SSD) with in-flight erasure iteration suspension

A data structure is maintained for performing a program operation that is allowed to be suspended to perform reads in a NAND device, where the data structure indicates a plurality of tiers, where each tier of the plurality of tiers has a number of allowed suspends of the program operation while executing in the tier, and where a sum of the number of allowed suspends for all tiers of the plurality of tiers equals a maximum allowed number of suspends of the program operation. In response to performing a resume of the program operation, after performing a read following a suspend of the program operation, a determination is made of a tier of the plurality of tiers for the program operation and a subsequent suspend of the program operation is performed only after a measure of progress of the program operation has been exceeded in the determined tier.

Method, system, and apparatus for multi-tiered progressive memory program operation suspend and resume

Independent multi-plane commands for non-volatile memory devices are described. In one example, a three-dimensional (3D) NAND memory device includes 3D NAND dies, each die including multiple planes of memory cells. The device includes input/output (I/O) circuitry to receive multiple commands from a host, each of the received commands to access one of the planes. The device includes logic (which can be implemented with, for example, an ASIC controller, firmware, or both) to queue the commands in separate queues for each of the planes based on a target plane of each of the commands. The logic issues the commands to their target planes independent of other planes' status, and tracks completion status of the commands independently for each plane.

Independent NAND memory operations by plane

An example apparatus includes a non-volatile memory including a first memory having a first write rate and a second memory having a second write rate, the first write rate greater than the second write rate An example controller is to determine, based on a ratio, a first portion of the data to be written to the first memory, and a second portion of the data to be written to the second memory type, the second portion of the data not included in the first portion of the data.

Methods and apparatus to configure performance of a solid state drive based on host write bandwidth

Examples described herein can be used to reduce a number of re-read operations and potentially avoid data recovery operations, which can be time consuming. A determination can be made of a read voltage to apply during an operation to cause a read of data stored in a region of a memory device. The region of the memory device can be read using the read voltage. If the region is not successfully read, then an error level indication can be measured and a second read voltage can be determined for a re-read operation. If the re-read operation is not successful, then a second error level indication can be measured for the re-read operation. A third read voltage can be selected based on the change from the error level indication to the second error level indication.

Techniques to a set voltage level for a data access

A refreshing method is described. The method includes recognizing a set of blocks of a non-volatile memory for refreshing and then refreshing a subset of the data within the blocks, where, invalid data within the blocks is not recognized for refreshing and a group of blocks whose oldest data has not aged for a pre-set time period is not recognized for refreshing.

Non volatile mass storage device with improved refresh algorithm

An embodiment of a semiconductor apparatus may include technology to determine an error rate associated with a read request for a persistent storage media, compare the determined error rate against a pre-fail threshold, and adjust a read voltage shift direction for the persistent storage media if the determined error rate exceeds the pre-fail threshold. Other embodiments are disclosed and claimed.

Proactive reduction of re-read triggering

An embodiment of a semiconductor apparatus may include technology to determine a differentiator associated with an access request for two or more memory devices, and set a target order for the two or more memory devices based on the differentiator. Other embodiments are disclosed and claimed.

Ordering of memory device mapping to reduce contention

A first type of command is suspended, by a controller of a non-volatile memory device, in response to determining that a second type of command is waiting for execution. The first type of command is split into a plurality of chunks based on a computed criteria. A second type of command is executed in between execution of at least two chunks of the first type of command.

Method, system, and apparatus for nested suspend and resume in a solid state drive

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San Jose, CA, United States of America

Xin Guo