International Business Machines Corporation

Vixs Systems, Inc.

Xin Guo

Reid T Copeland

Petra Leber

Eric M Schwarz

Jonathan D Bradbury

Silvia Melitta Mueller

Cedric Lichtenau

Kerstin Claudia Schelm

Timothy John Slegel

Michael Klein

Qi Yang

Indra Laksono

Xu Gang Zhao

Wendy Wai Yin Cheung

Bruce C Giamei

Stefan Payer

Andreas Wagner

Bonnie Kathryn Ray

Edward Hong

Xinghai Li

Eric Young

Chun-Chin David Yeh

Quoc-Bao Nguyen

An instruction to perform validity testing of a source value is executed. The executing the instruction includes obtaining the source value using at least one field of the instruction and obtaining a plurality of test controls using a field of the instruction. The one or more test controls of the plurality of test controls are used to specify which digit positions of the source value are to be tested for validity and what codes are valid codes for the digit positions specified to be tested. Validity testing of at least a portion of the source value is performed based on the plurality of test controls obtained using the field of the instruction, and the performing the validity testing provides a result. The result is provided for use in further processing.

Vector test decimal instruction for validity testing

An instruction to perform converting and scaling operations is provided. Execution of the instruction includes converting an input value in one format to provide a converted result in another format. The converted result is scaled to provide a scaled result. A result obtained from the scaled result is placed in a selected location. Further, an instruction to perform scaling and converting operations is provided. Execution of the instruction includes scaling an input value in one format to provide a scaled result and converting the scaled result from the one format to provide a converted result in another format. A result obtained from the converted result is placed in a selected location.

Vector convert hexadecimal floating point to scaled decimal instruction

An instruction to perform an operation selected from a plurality of operations configured for the instruction is executed. The executing includes determining a value of a selected operand of the instruction. The determining the value is based on a control of the instruction and includes reading the selected operand of the instruction from a selected operand location to obtain the value of the selected operand, based on the control having a first value, and using a predetermined value as the value of the selected operand, based on the control having a second value. The value and another selected operand of the instruction are multiplied to obtain a product. An arithmetic operation is performed using the product and a chosen operand of the instruction to obtain an intermediate result. A result from the intermediate result is obtained and placed in a selected location.

Hexadecimal floating point multiply and add instruction

Vector pack and unpack instructions are described. An instruction to perform a conversion between one decimal format and another decimal format is executed, in which the one decimal format or the other decimal format is a zoned decimal format. The executing includes obtaining a value from at least one register specified using the instruction. At least a portion of the value is converted from the one decimal format to the other decimal format different from the one decimal format to provide a converted result. A result obtained from the converted result is written into a single register specified using the instruction.

Vector pack and unpack instructions

An instruction to perform scaling, converting and splitting operations is executed. The executing the instruction includes scaling an input value in one format to provide a scaled result. The scaled result is converted from the one format to provide a converted result in another format. The converted result is split into multiple parts, and one or more parts of the multiple parts are placed in a selected location.

Decimal scale and convert and split to hexadecimal floating point instruction

Digit validation check control for execution of an instruction. A process obtains an instruction to perform operation(s) using input value(s). The instruction includes a no validation indicator for controlling whether digit validation check control is enabled for execution of the instruction. The process executes the instruction, including determining, based on the no validation indicator, whether digit validation check control is enabled for execution of the instruction, and performing processing based on the determining. Based on the no validation indicator being set to a defined value, digit validation check control is enabled and the processing includes forcing a digit check error indicator output by the executing to indicate no digit check error with respect to the at least one input value.

Digit validation check control in instruction execution

Negative zero control for execution of an instruction. A process obtains an instruction to perform operation(s) using an input value. The instruction includes a negative zero control indicator indicating whether negative zero control is enabled for execution of the instruction. The process executes the instruction, the executing including performing the operation(s) using the input value to obtain a result having a sign, determining whether to control the sign of the result, the determining being based at least in part on the negative zero control indicator being set to a defined value, and performing further processing, as part the executing the instruction, based on the determining.

Negative zero control in instruction execution

Each set of pels of an image frame is encoded into a corresponding set of codewords having fixed-length and unary variable-length components. The variable-length components are combined into a variable-length portion and the fixed-length components are separately combined into a fixed-length portion that is attached to the variable-length portion to complete a bit segment. For decompression, a first bit string of a fixed number of bits is identified as a fixed-length portion of the bit segment. A search window placed adjacent to the first bit string is scanned to find a second bit string having a number of termination bits equal to the number of codewords in the set, with the second bit string thus representing the variable-length portion of a corresponding bit segment. Each variable-length component of the identified variable-length portion is combined with a corresponding fixed-length component of the identified fixed-length portion to recreate a corresponding codeword.

Frame buffer compression using separate aggregation of fixed-length and variable-length components of codewords

Reference pictures received via a video signal are downscaled to a specified resolution by a video encoder/decoder. For each current picture being processed by the video encoder/decoder, the current picture is maintained at its original received resolution, but is divided into blocks. Each block is further divided into sub-blocks, and each sub-block is compared, for a set of specified positions, to a corresponding block of the downscaled reference image to generate a set of candidate motion vectors. The candidate motion vectors are scored according to how closely their corresponding sub-block matches the corresponding block of the reference picture at the corresponding position, and a motion vector for each block of the current image is selected based on the scores. The selected motion vectors are used to process (e.g. encode) the video signal.

Motion search with scaled and unscaled pictures

A video processing device includes a video processing unit that decodes a video input signal into a decoded video signal in accordance with a video compression protocol, based on uncompressed video frame data. A data object compression/decompression module generates compressed video frame data by compressing a plurality of video data objects into a plurality of compressed video data objects, storing the plurality of compressed video data objects in a compressed frame buffer. The data object compression/decompression module retrieves a selected portion of video frame data from the compressed video frame buffer by identifying selected ones of plurality of compressed video data objects that correspond to the selected portion of video frame data, retrieving the selected ones of the plurality of compressed video data objects and generating the uncompressed video frame data by decompressing the selected ones of the plurality of compressed video data objects.

Video processor with random access to compressed frame buffer and methods for use therewith

A video processing device includes a video processing unit that decodes a video input signal into a decoded video signal in accordance with a video compression protocol, based on uncompressed video frame data. A tile engine includes a tile accumulation module that accumulates the uncompressed video frame data into a plurality of tile units, wherein each of the plurality of tile units includes a plurality of video span units. A tile compression/decompression module generates compressed video frame data for storage in a compressed video frame buffer by compressing the plurality of video span units into a plurality of compressed video span units and further that retrieves the compressed video frame data from the compressed video frame buffer by retrieving the plurality of compressed video span units and generating the uncompressed video frame data by decompressing the plurality of compressed video span units.

Video processor with reduced memory bandwidth and methods for use therewith

A video processing device includes a video processing unit that decodes a video input signal into a decoded video signal in accordance with a video compression protocol, based on uncompressed video frame data. A data object compression/decompression module generates compressed video frame data for storage in a compressed video frame buffer by compressing a plurality of video data objects into a plurality of compressed video data objects, wherein a first subset of the plurality of video data objects are compressed via lossless compression and a second subset of the plurality of video data objects are compressed via lossy compression.

Video processor with lossy and lossless frame buffer compression and methods for use therewith

A method and structure for performing a negotiation on a computer network, including initiating an auction and determining whether a Pareto-Optimal point is satisfied for the auction.

Method, computer network, and signal-bearing medium for performing a negotiation utilizing pareto-optimization

A method (and structure) of optimizing a sampling period for a system having at least one measurable system parameter z, includes calculating a probability distribution function f(T). The time Tis a first time that the measurable system parameter z will reach a predetermined system threshold x, given level z.

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Toronto, Canada

Xin Guo